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Advance Computer Architecture (CS501)

Assignment#02 (GRADED)

  Total marks = 20

                                                                                       Deadline Date = 23-05-2017


Please carefully read the following instructions before attempting the assignment.

Assignment Guidelines:

It should be clear that your assignment would not get any credit if:

  • The assignment is submitted after due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is copied. Note that strict action would be taken if the submitted assignment is copied from any other student. Both students will be punished severely.


1)      You should consult recommended books to clarify your concepts as handouts are not sufficient.

2)      You are supposed to submit your assignment in .doc or .docx format. Any other formats like scan images, PDF, Zip, rar, bmp etc will not be accepted.

3)      You are advised to upload your assignment at least two days before due date.

Important Note: 

Assignment comprises of 20 Marks. Note that no assignment will be accepted after due date via email in any case (whether it is the case of load shedding or emergency electric failure or internet malfunctioning etc.). Hence, refrain from uploading assignment in the last hour of the deadline, and try to upload Solutions at least 02 days before the deadline to avoid inconvenience later on.

For any query please contact: CS501@vu.edu.pk


The objective of this assignment is to assess understanding of,

  • Structural RTL for the FALCON-A instructions
  • External FALCON-A CPU Interface
  • Control Signals Generation in FALCON-A





What will be the logic levels on the external FALCON-A buses when each of the given FALCON-A instruction is executing on the processor? Complete the table given. All numbers are in the decimal number system.



v  All memory content is aligned properly.

  • In other words, all the memory accesses start at addresses divisible by 2.
  • Value in the PC = 0212 h


Note: FALCON-A uses the big-endian storage format



RTL equivalent

Address Bus


Data Bus




load R6, [R5+16]






store R7, [R2+12]






asr R1, R3, 5






div R6, R5, R1






jnz R2, [26]






shiftl R4, R6, 9






load R0, [R4-21]






store R1, [R6-64]













Memory map with assumed values:

Memory Address

Memory Content

0100 h

AC h

0101 h

21 h

0102 h

3E h

0103 h

D2 h



0A50 h

1E h

0A51 h

C5 h

0A52 h

99 h

0A53 h

52 h

Memory Address

Memory Content

AB60 h

26 h

AB61 h

A1 h

AB62 h

92 h

AB63 h

12 h



EF40 h

19 h

EF41 h

30 h

EF42 h

41 h

EF43 h

F2 h


Register map with assumed values:

Register Name



5CB6 h


20B6 h


00F4 h


4141 h


0A65 h


AB50 h


EF80 h





Good Luck

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Lecture 7 and 8 will be helpful to solve this assignment

Imhum if you solved the assignment kindly share the solution please.

Due date extend to 24-05-2017

boys and girls.

today is the last date please share the idea solution to solve this assignment

Few hours left please share the solution.

:P dosto buzurgo koi to himat kry :)


is it right solution?

LMS open nahi ho rha. assignment kasy submit karin?


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