.... How to Find Your Subject Study Group & Join ....   .... Find Your Subject Study Group & Join ....  

We are here with you hands in hands to facilitate your learning & don't appreciate the idea of copying or replicating solutions. Read More>>

Study Groups By Subject code Wise (Click Below on your university link & Join Your Subject Group)

[ + VU Study Groups Subject Code Wise ]  [ + COMSATS Virtual Campus Study Groups Subject Code Wise ]

Looking For Something at vustudents.ning.com?Search Here

CS501_Share your Current Mid Term Papers Spring 2017 at One Place from 03 June 2017 to 14 June 2017.

CS501_ ALL Current Mid Term Papers

Fall 2017 at One Place

from 03 June 2017 to 14 June 2017.  

 

For Important Helping Material related to this subject (Solved MCQs, Short    Notes,  Solved past Papers, E-Books, FAQ,Short Questions Answers &  more)View Featured discussions.

 For view all the Featured discussions click on the Back to Subject Name  Discussions link below the title of this Discussion & then under featured  Discussion corner click on the view all link.

 Or visit this link 

  Click Here For Detail.

 

  Solutions for not opening files..
 

  PDF Files downloading Solution from ning..

 
Problem in downloading PDF files..

 

Share This With Friends......


How to Find Your Subject Study Group & Join.

Find Your Subject Study Group & Join.

+ Click Here To Join also Our facebook study Group.


This Content Originally Published by a member of VU Students.

+ Prohibited Content On Site + Report a violation + Report an Issue

+ Safety Guidelines for New + Site FAQ & Rules + Safety Matters

+ Important for All Members Take a Look + Online Safety


Views: 1093

See Your Saved Posts Timeline

Replies to This Discussion

Share Your Current Mid Term Papers (Questions/Pattern) & Past Papers as well here to help each other. Thanks 

Note:-

For Important Helping Material related to this subject (Solved MCQs, Short Notes, Solved past Papers, E-Books, FAQ,Short Questions Answers & more). You must view all the featured Discussion in this subject group.

For how you can view all the Featured discussions click on the Back to Subject Name Discussions link below the title of this Discussion & then under featured Discussion corner click on the view all link.

Or visit this link 

Click Here For Detail.

&

.•°How to Download past papers from study groups°•.

 

Please Click on the below link to see…

.... How to Find Your Subject Study Group & Join .... 

18 MCQ's. All MCQ's form moaz
5 Subjective Question
subjective question these are following:

1) Give three examples of processors that are superscaler architecture? 3 Marks
2) How do we refer to the registers in RTL? Given an examples? 3 Marks
3) What do you know about a register-memory machine? Also write two advantages and two disadvantages of using this machine? 3 Marks
4) Briefly explain data dependence complication related to piplining? Also give example? 5 Marks
5) In condition jump, How do we test the condition? 5 Marks

Attachments:

MCQS are almost from past pprz

1)SRC For sub ra,rb,rc

2)SRC for in ra,c2

3)two advantages of the linker

4)condition jumps

5)Arithmatic tha 3 adress or 2 adress sa related

 

 +@mna BSCS* thanks for sharing 

CS501 Current Midterm Paper

1) Give three examples of processors that are superscalar architecture? 3 Marks

Answer:

Superscalar Processors

Examples of superscalar processors
1. PowerPC 601
2. Intel P6
3. DEC Alpha 21164


2) How do we refer to the registers in RTL? Given an example? 3 Marks

Answer:







3) What do you know about a register-memory machine? Also write two advantages and two disadvantages of using this machine? 3 Marks

Answer:

Register-memory machines
In register-memory machines, some operands are in the memory and some are in registers. These machines typically employ 1 or 1. Address instruction format, in which one of the operands is an accumulator or a general-purpose CPU registers.

Advantages
Register-memory operations use one memory operand out of a total of two operands. The advantages of this instruction format are
• Operands in the memory can be accessed without having to load these first through a separate load instruction
• Encoding is easy due to the elimination of the need of loading operands into registers first

Disadvantages
• Operands are not equivalent since one operand may have two functions (both source operand and destination operand), and the source operand may be destroyed
• Different size encoding for memory and registers may restrict the number of registers
• The number of clock cycles per instruction execution vary, depending on the operand location operand fetch from memory is slow as compared to operands in
CPU registers

4) Briefly explain data dependence complication related to pipelining? Also give example? 5 Marks

Answer:

Data dependence
This refers to the situation when an instruction in one stage of the pipeline uses the results of an instruction in the previous stage. As an example let us consider the following two instructions

S1: add r3, r2, r1
S2: sub r4, r5, r3

5) In condition jump, how do we test the condition? 5 Marks

Answer:

How do we test the condition?
This is tested by the contents given by the register ra. So condition within square brackets is R[ra]. This means test the data given in register ra. There are different possibilities and so the data could be positive, negative or zero. For this particular instruction it would be tested if the data were zero. If the data were zero, the “CON” would be 1.
In T4 we just take the contents of the PC into the buffer register A. In T5 we add up the contents of A to the constant c2 after sign extension. This addition will give us the effective address to which a jump would be taken. In T6, this value is copied to the PC.
In FALCON-A, the number of conditional jumps is more than in SRC. Some of which are shown below:
• jz (op-code= 19) jump if zero
jz r3, [4] (R[3]=0): PC← PC+ 2;
• jnz (op-code= 18) jump if not zero
jnz r4, [variable] (R[4]≠0): PC← PC+ variable;
• jpl (op-code= 16) jump if positive
jpl r3, [label] (R[3]≥0): PC ← PC+ (label-PC);
• jmi (op-code= 17) jump if negative
jmi r7, [address] (R[7]<0): PC← PC+ address;

Today paper cs501
what r the key components for defining any instruction set architecture(ISA).
Difference between Latency and Throughput.
UniBus path implimentation of the SRC boolian execution.
thry give a circuit....
Five differences RICS and CISC

cs501..... today paper 


all mcq's frompast papers moaz and waqar files ... 


subjective ..


differnce bw computer organization and computer architecture
MAR and MBR
table ........ instructions given we have to told pc status
what r the key components for defining any instruction set architecture(ISA).
dependent complication related to pipelining . with example ..

Upload waqar mcqs files.

Difference b/w computer organization and computer architecture
Answer:
Computer organization is concerned with the way the hardware components operate and the way they are connected together to form computer system while comp architecture is concerned with the structure and behavior of comp system as seen by the user. It includes information, formats, instruction set and techniques for addressing memory

MAR and MBR
Answer:

MAR
The Memory Address Register takes input from the ALSU as the address of the memory location to be accessed and transfers the memory contents on that location onto the memory sub-system.
MBR
The Memory Buffer Register has a bi-directional connection with both the memory sub-system and the registers and ALSU. It holds the data during its transmission to and from memory.

What r the key components for defining any instruction set architecture (ISA).
Answer:
Three key components define any instruction set architecture.
1. The operations the processor can execute
2. Data access mode for use as operands in the operations defined
3. Representation of the operations in memory

Dependent complication related to pipelining. With example...
Answer:
Complications Related to Pipelining
Certain complications may arise from pipelining a processor. They are explained below:
Data dependence
This refers to the situation when an instruction in one stage of the pipeline uses the results of an instruction in the previous stage. As an example let us consider the following two instructions

S1: add r3, r2, r1
S2: sub r4, r5, r3

Hi friends

I have made a mega file which includes moaz, quizes and waqar sidhus file

koshish ki hy tamam ko confirm krny ki lakin agar koi ghalti ho to khud thek kr liajaey ga

I wish you best of luck

RSS

Forum Categorizes

Job's & Careers (Latest Jobs)

Admissions (Latest Admissons)

Scholarship (Latest Scholarships)

Internship (Latest Internships)

VU Study

Other Universities/Colleges/Schools Help

    ::::::::::: More Categorizes :::::::::::

Member of The Month

1. + ! ! ! ! ϝιƴα ^

Venice, Italy

© 2018   Created by + M.Tariq Malik.   Powered by

Promote Us  |  Report an Issue  |  Privacy Policy  |  Terms of Service