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Assignment No. 02 Semester: Spring 2013 CS501: Advanced Computer Architecture,Total Marks: 20 Due Date: 06-05-13

Assignment No. 02
Semester: Spring 2013

CS501: Advanced Computer Architecture

                                                              Total Marks: 20

Due Date:  06-05-13

Instructions

Please read the following instructions carefully before assignment submission.

 

 

It should be clear that your assignment will not get any credit if:

 

  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is found to be copied from the internet.
  • The assignment is found to be copied from other student.
  • The assignment submitted is not according to required file format (.doc).

 

 

Objective

The objective of this assignment is:

 

  • To assess your overall understanding of Register Transfer Language and its notations.
  • To assess your overall understanding of binary encoding of Computer Instructions.
  • To assess your overall understanding of how data is being processed in Registers and memory.

 

 

 

Note:

 

  • The assignment should be in .doc format.
  • Assignment .02 covers lecture 6-10. You can also consult reference books for help.
  • Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

 

 

 

Question No 1:                                                 Marks 1+1+1+1+1=5

  Q. 1.                        Briefly explain the following Register Transfer Language (RTL) notations:

 

1)    R [1]           ß  R [2] + (-56)

2)   R[5] ←R[0] ©R[6]/R[3]

3)   R [4] ß  R [3] ~ R [1]

4)   IO[R [4]+1]ß  R[7]]

5)   M[R [1] +13]    ß   R [3]

 

 

Question No 2: Fill the given table by specifying binary encoded values against each instruction.                                                               

Marks 15

Instruction

Type

OP-Code

Ra

Rb

Rc

C1

C2

Addressing mode

RTL Description

Condition

PC status

ori r2, r4, 9

 

 

 

 

 

 

 

 

 

 

 


jnz r1, [27]

 

 

 

 

 

 

 

 

 

 

 

 

Out  7,R5(30)

 

 

 

 

 

 

 

 

 

 

 

Load R[6]+99]

 

 

 

 

 

 

 

 

 

 

 

Jmi  R3,[7]

 

 

 

 

 

 

 

 

 

 

 

 

Note: You may write N/A in a cell not relevant to any instruction.

 

 

                                              GOOD LUCK!

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Replies to This Discussion

Hey BFSS,

Thank You for sharing the solution of Q 2. 

i want to clarify one thing. In this instruction  Jmi  R3,[7]

You mentioned the RTL Description = 

R[1]<0

PC←PC+7 

& i think it should be 

R[3]<0

PC←PC+7

because the value of register is R3.

Correct me if i am wrong.

Thanks

Also, in the out instruction

Out 7,R5(30)

I think it's Type should be C and Op-code = 7

Reference is in Lec 9

Also, in the out instruction

Out 7,R5(30)

falcon-A mai opcode= 25

Falcon-e mai opcode for out instruction = 7

but 7 given in the instruction is not a constant it refers to register no 7

BFSS,

I know 7 is not a constant. Please read lec 9 and check the below example that is in Lec 9

out(op-code = 7)
This instruction is used to write / store the register contents into an input/output
device. Again, the effective address calculation has to be carried out to evaluate
the destination I/O address before the write can take place. For example,
out R8, R6 (36)
RTL representation of this is
IO[R [6]+36] ← ←← ←R [8]
Three of the ALU instructions that belong to typeC format are

Mehreen thanks 

thanks, i have already said that plz check and also tell me if there is any mistake

3

 my question is whether the given instruction Out  7,R5(30) given in the Question no. 2  is correct or not ???????????????

 

IO[R [4]+1]ß  R[7]] what about this BFSS ?????????  is it

The contents of the register r7 are being stored to the memory location that corresponds to the sum of the constant 1 and the ‘out’ instruction will move data to the out put device specified in the instruction.

is it correct ????? BFSS please discuss it

this instruction is similar to out instruction, contents of the R7 will move to the output device specified by the adding contents of the register R[4] and  const 1.

Register Transfer Language (RTL)


RTL

RTL is a simple, human-oriented language to specify the operations, register communication and timing of the steps that take place within a CPU to carry out higher level (user programmable) instructions.

A step is the unit of operation done in one clock cycle.

Parallel and Serial operations are possible at this level. Some operations can be done in other parts of the CPU simultaneously--they are independent of each other. Other operations must follow in sequence because of dependencies.

Parallel Operations: Place the operations on the same line and separate with semicolons. These operations are done in the same clock cycle.
operation1; operation2;...

Serial: Just sequence the operations on subsequent lines. Each operation takes a clock cycle.
op1
op2

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