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Assignment No. 02 Semester: Spring 2013 CS501: Advanced Computer Architecture,Total Marks: 20 Due Date: 06-05-13

Assignment No. 02
Semester: Spring 2013

CS501: Advanced Computer Architecture

                                                              Total Marks: 20

Due Date:  06-05-13


Please read the following instructions carefully before assignment submission.



It should be clear that your assignment will not get any credit if:


  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is found to be copied from the internet.
  • The assignment is found to be copied from other student.
  • The assignment submitted is not according to required file format (.doc).




The objective of this assignment is:


  • To assess your overall understanding of Register Transfer Language and its notations.
  • To assess your overall understanding of binary encoding of Computer Instructions.
  • To assess your overall understanding of how data is being processed in Registers and memory.






  • The assignment should be in .doc format.
  • Assignment .02 covers lecture 6-10. You can also consult reference books for help.
  • Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.




Question No 1:                                                 Marks 1+1+1+1+1=5

  Q. 1.                        Briefly explain the following Register Transfer Language (RTL) notations:


1)    R [1]           ß  R [2] + (-56)

2)   R[5] ←R[0] ©R[6]/R[3]

3)   R [4] ß  R [3] ~ R [1]

4)   IO[R [4]+1]ß  R[7]]

5)   M[R [1] +13]    ß   R [3]



Question No 2: Fill the given table by specifying binary encoded values against each instruction.                                                               

Marks 15









Addressing mode

RTL Description


PC status

ori r2, r4, 9












jnz r1, [27]













Out  7,R5(30)












Load R[6]+99]












Jmi  R3,[7]













Note: You may write N/A in a cell not relevant to any instruction.



                                              GOOD LUCK!

Views: 5457


Replies to This Discussion

Sari asignment Lecture 7 sy hi related hy??????? mn aj sy krny lgi

Question 2 mn kya hm logon ny asy hi program likhna hy or falcon-A mn execute krna hy?

; testdiv.asfma  this is a program to test the divide instruction
.org 100
movi r1,2
add r2,r3


jz r0,[3]

bekasoora na mara jaen first question idr enter to kr koi to btae ga

  + (♥╣✿JoB SeEkEr:'( ✿╠♥) +

no need to execute statements , just explain the given instruction's working in simple english text ...

plxxxxxxxxxxxx koi question no 1 ka b bta dy

Question No 1:
1) R [1]  R [2] + (-56) 
This instruction is to add a constant value (-56) to a register r2; the result is stored in a destination register r1. Its op-code=1.

2) R[5] ←R[0] ©R[6]/R[3]  
This instruction will devide the value of the register r6 that is the second operand, by the number in the register r3 specified by the third operand, and assign the result to the destinatin register r5. Its op-code=5.

3) R [4]  R [3] ~ R [1]  
 ‘or’ instruction is used To bit-wise the contents of two registers r3 and r1, and result is stored in destination register r4. Its op-code is=10.

4) IO[R [4]+1] R[7]] 
The out instruction will move data from the register r(4)+1 to the output device specified in the instruction i.e r7. Its op-code=25.

Muhammad zubair thanks for sharing ur idea ..keep it up

Note for All Members: You don’t need to go any other site for this assignment/GDB/Online Quiz solution, Because All discussed data of our members in this discussion are going from here to other sites. You can judge this at other sites yourself. So don’t waste your precious time with different links.

Muhammad zubair thanx alot 

Oka thx BFSS sis

1)  R [1]  ß  R [2] + (-56)

constant 56 is subtracted from the value stroed in register r2 and result is stored in register r1

2)    R[5] ←R[0] ©R[6]/R[3]

the value of register r0 and r6 is concatenated and devided by the value of the register r3. the result is stored in register r5.

R [4] ß  R [3] ~ R [1]

logical Or the values of register r3 and r1 and result is stored in register r4.


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