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Assignment No. 02
Graded Assignment)
Semester: Fall 2013

CS501: Advanced Computer Architecture



Total Marks: 20

Due Date
5 December, 2013 



Please read the following instructions carefully before assignment submission.

It should be clear that your assignment will not get any credit if:

  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is found to be copied from the internet.
  • The assignment is found to be copied from other student.
  • The assignment submitted is not according to required file format (.doc).


The objective of this assignment is:

  • To assess your overall understanding of Computer Architecture and Organization.
  • To assess your overall understanding of RTL (Register Transfer Language) instructions.
  • To assess your overall understanding of Fetch, Decode and Execute Cycle clock in CPU.



  • The assignment should be in .doc format.
  • Assignment .02 covers lecture 8-14. You can also consult reference books for help.
  • Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

Question 1:                                                                                     Marks 15

Suppose you have eight general purpose registers ( ra, rb, rc, rd, re, rf, rg and rh). You are required to complete the instruction fetch-execute cycle of register-to-register sub (subtract) and add (addition) instructions. Also specify the corresponding type of structural RTL.

You are required to solve:

1.1.   Type of structural RTL (Register Transfer Language)                               1 Mark

1.2.   Fetch-execute cycle of the register-to-register Add instruction                    7 Marks

1.3.   Fetch-execute cycle of the register-to-register Sub instruction             7 Marks


Question  2:                                                                 Marks 1+1+1+1+1=5


          Briefly explain the following RTL (Register Transfer Language) notations                                              i.            R [4] ß  R [3] + (-32)

                                                          ii.            R[2] ←R[0] ©R[5]/R[7]

                                                          iii.            R [1] ß  R [2] ~ R [5]

                                                          iv.            IO[R [2]+1]ß  R[1]]

                                                          v.            M[R [2] +14]    ß   R [4]


Views: 8621


Replies to This Discussion

as far as i have understood it the fetch instructions are same as in the book then for execute instruction as given for 3 registers we have to extend it to 8 register like




and so on to the 8th register. if anyone have better understanding write it

dear agr esy bnaye tu upto  rh steps T7 sy increase kr jaaty hein

but A and C are used for 3 registers and not mentioned anywhere if steps can not go any further than T7 right?

or is me A, C hi use hun gy q k lec 12 me diagram ko ghoor sy dykhein 

R[2] ←R[0] ©R[5]/R[7] is instruction ko explain kar de koi

Contents of register R5 are devided by the R7, the division is concatenated with R0 and then result stored in R2

Q.2 is easy.

Q.1 in this question make a table in which show the timing steps and functions accordingly. this is in in lecture 12 also given. same copy and the solution is in your hand

thanx for your share,

we are benefitting a lot.

Please post the answer of Q2 MR.Sajjad.

Ali Muaaz 8 minutes ago.


  Briefly explain the following RTL (Register Transfer Language) notations:                                                       

  1.     i.        R [4] ß  R [3] + (-32)

The contents of the registers r3 are added with -32 and the result is stored in the register r4.

  2.        ii.        R[2] ←R[0] ©R[5]/R[7]

Contents of register r5 are divided by the value stored in r7, result is concatenated with 0s, and stored in r2.

  2.           iii.        R [1] ß  R [2] ~ R [5]

Logical OR of the contents of the registers r2 and r5 is obtained and the result is stored in register r1

  2. iv.        IO[R [2]+1]ß  R[1]]

An output of the register r1 is sent to an output device (where the address of the output device is specified by the sum of the constant 1 and the value stored in the register r2


  2.      v.        M[R [2] +14]    ß   R [4]

The contents of the register r4 are being stored to the memory location that corresponds to the sum of the constant 14 and the value stored in the register r2

Divide the contents of register R5 with the contents of register R7 and transfer the result into the register R2 after concatenating the contents of register R0

kaya hum q1 may registers ko register k sath add yan sub kar saktay han.please koe reply day do


add ra,rb,rc,rd,re,rf,rg,rh

fetch step




MAR – PC – PC+4






sub ra,rb,rc,rd,re,rf,rg,rh
Fetch Step




MAR – PC – PC+4







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