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# CS501 ASSIGNMENT NO. 5, DISCUSSION AND SOLUTION( DUE DATE: 3RD JULY, 2013)

Plz Discuss this assignment

 Assignment No. 05 Semester: Spring 2013 CS501: Advanced Computer Architecture Total Marks: 20 Due Date:  03-07-13 Instructions Please read the following instructions carefully before assignment submission. It should be clear that your assignment will not get any credit if: The assignment is submitted after the due date. The submitted assignment does not open or file is corrupt. The assignment is found to be copied from the internet. The assignment is found to be copied from other student. The assignment submitted is not according to required file format (.doc). Objective The objective of this assignment is: To assess your overall understanding of Computer Architecture and Organization To assess your overall understanding of Computer processing To assess your overall understanding of DMA, Polling and interrupts Note: The assignment should be in .doc format. Assignment .05 covers lecture 25-31. You can also consult reference books for help. Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

Question No 1:
(10 marks)

Suppose we have a benchmark that executes in 100 seconds of elapsed time, where 90 seconds is CPU time and the rest is I/O (Input/output) time. If CPU time improves by 50% per year for the next five years but I/O time doesn’t improve, how much faster will our program run at the end of five years?

You are required to calculate the CPU improved performance and improved elapsed time.

 After n years CPU/ time I/O time Elapsed time % I/O time 0 (Current Year) 1 2 3 4 5

NOTE: Theoretical answer will not be considered

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Question No 2:                                                                                                      (4 marks)

Consider a 20 MIPS (Microprocessor without Interlocked Pipeline Stages) processor with several input devices attached to it, each running at 1000 characters per second. Assume that it takes 17 instructions to handle an interrupt. If the hardware interrupt response takes 1msec, what is the maximum number of devices that can be handled simultaneously?

NOTE: Theoretical answer will not be considered

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Question No 3:                                                                                                        (6 Marks)

Scenarios discussion:

If we want the lowest latency for an I/O operation to a single I/O device; while in terms of lowest impact on processor utilization from a single I/O device then what will be the orders/arrangements of Interrupt driven, DMA(Direct Memory Access) and polling in both scenarios? Explain reasons.

NOTE: Give answer within 3-5 lines. Otherwise answer will not be considered.

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GOOD LUCK J

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### Replies to This Discussion

system improvement 100/22 mn 22 kahan sy aya?Sana Rajpoot plz explain sis

yar ye 1.5 kaha se aata ha

yar ye denominator main har bar 1.5 kaha se aata ha????

•  in Q no3 we have to give  order of 3 methods given in bold letters(Interrupt driven, DMA and polling)  for 2 scenarios

scenario no 1.If we want the lowest latency for an I/O operation to a single I/O device;

scenario no 2. while in terms of lowest impact on processor utilization from a single I/O device

•  and to Explain reasons of selecting that order/arrangement of (Interrupt driven, DMA and polling) in 3-5 lines

i hope q no 3 will be clear now every one can answer.

read lect 26, 27, 28, 31  and conclude your answer in 3-5 lines

Good effort .   Thanx BFSS sis

no need to say thanks bas dua ker dia karin dunyia aur akhirat  main kamyabi aur kamrani ki

Allah hum sab ko dunyia aur akhirat  main kamyabi aur kamrani ata farmai...! Ameen

Q #2 ki example ki calculation theek ni hui. kindly calculation kr k chk kr lain

and BFSS sis agar ap Q # 3 ki arrangements just bta dain to maharbani ho gi, comments hm khud explain kr lain gay

##### Interrupt Driven: An I/O scheme that employs interrupts to indicate to the processor that an I/O device needs attention.

DMA: A mechanism that provides a device controller with the ability to transfer data directly to or from the memory without involving the processor.

##### Polling: The process of periodically checking the status of an I/O device to determine the need to service the device.

For Q 3 i found,

1. Polling

2. Interrupt Driven I/O

3. DMA

If i am wrong plz correct me with reason??? m waiting........

i think DMA is first and than Interrupt driven because DMA has higher priority than interrupt

i think the order wud b

1. DMA

2. polling

3. Interrupt Driven I/O

firstly DMA uses less CPU n then polling involves less CPU comparitively n then Interrupt driven....

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