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Assignment No. 05
Semester: Spring 2013

CS501: Advanced Computer Architecture



Total Marks: 20

Due Date:  03-07-13



Please read the following instructions carefully before assignment submission.

It should be clear that your assignment will not get any credit if:

  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is found to be copied from the internet.
  • The assignment is found to be copied from other student.
  • The assignment submitted is not according to required file format (.doc).


The objective of this assignment is:

  • To assess your overall understanding of Computer Architecture and Organization
  • To assess your overall understanding of Computer processing
  • To assess your overall understanding of DMA, Polling and interrupts


  • The assignment should be in .doc format.
  • Assignment .05 covers lecture 25-31. You can also consult reference books for help.
  • Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.





Question No 1:
                                                                                                     (10 marks)

Suppose we have a benchmark that executes in 100 seconds of elapsed time, where 90 seconds is CPU time and the rest is I/O (Input/output) time. If CPU time improves by 50% per year for the next five years but I/O time doesn’t improve, how much faster will our program run at the end of five years?

You are required to calculate the CPU improved performance and improved elapsed time.    

After n years

CPU/ time

I/O time

Elapsed time

% I/O time

0 (Current Year)






























NOTE: Theoretical answer will not be considered


Question No 2:                                                                                                      (4 marks)

Consider a 20 MIPS (Microprocessor without Interlocked Pipeline Stages) processor with several input devices attached to it, each running at 1000 characters per second. Assume that it takes 17 instructions to handle an interrupt. If the hardware interrupt response takes 1msec, what is the maximum number of devices that can be handled simultaneously?

NOTE: Theoretical answer will not be considered


Question No 3:                                                                                                        (6 Marks)

Scenarios discussion:

If we want the lowest latency for an I/O operation to a single I/O device; while in terms of lowest impact on processor utilization from a single I/O device then what will be the orders/arrangements of Interrupt driven, DMA(Direct Memory Access) and polling in both scenarios? Explain reasons.

NOTE: Give answer within 3-5 lines. Otherwise answer will not be considered.




Views: 8064


Replies to This Discussion

Thx allz

how much faster our program run at the end of five year?

ok !


chavlay zayada marti hooo....

dosro ko tens krny k liyaaa.....

very bad sir faiz khan apki zuban pak ko bat pak krny ki tmeez pak nai hy 

Question no 2 is same as handouts

the question # 2 given in handouts and the question given in our assignment is same !! BFSS sister is right.

BFSS plzzz tell me the rite answerz!!!

which question ?

for q2

i think answer is correct in handout, plz compare ur statement of q no 2 in  ur assignment and handout. ok

us nay bola theorey nai chalnay wali :-(


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