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# CS302 Assignment No 03 Fall 2019 Solution & Discussion Due Date: 27-01-2020

CS302 Assignment No 03 Fall 2019 Solution & Discussion Due Date: 27-01-2020

 Digital Logic Design (CS302) Assignment # 03 Total marks = 20                                                                                 Deadline Date 27/01/2020 Please carefully read the following instructions before attempting assignment.   RULES FOR MARKING It should be clear that your assignment would not get any credit if: The assignment is submitted after the due date. The submitted assignment does not open or file is corrupt. Strict action will be taken if submitted solution is copied from any other student or from the internet.   You should concern the recommended books to clarify your concepts as handouts are not sufficient.   You are supposed to submit your assignment in .doc or docx format. Any other formats like scan images, PDF, zip, rar, ppt and bmp etc will not be accepted.   Topic Covered: ·         State Diagram ·         Counters ·         K-Maps ·       Circuit Design NOTE   No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date.   If you people find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline no queries will be entertained in this regard.   For any query, feel free to email at: cs302@vu.edu.pk

Questions No 01                                                                                                        Marks (20)

You are required to design a 4-bit even up-counter using D flip flop by converting combinational circuit to sequential circuit. The counter will only consider even inputs and the sequence of inputs will be 0-2-4-6-8-10-0.

You are required to perform following tasks:

1. Draw the State diagram.
2. Generate State & Transition Table.
3. Generate simplified Boolean Expression.
4. Design the final Circuit diagram.

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CS302 Assignment No 03 Solution Fall 20193

CS302_Assignmnet_03_Solution_Fall_2019_vustudents.ning.com.docx

tysm

CS302 Assignment No 03 Solution Fall 20193

CS302_Assignmnet_03_Solution_Fall_2019_vustudents.ning.com.docx

CS302 Assignment No 03 Solution Fall 2019

CS302-ASSIGNMENT-NO.docx

cs302assignmentno3.docx

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