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# CS302 Digital Logic Design Assignment No 03 Fall 2020 Solution & Discussion Due Date: 08-02-2021

CS302 Digital Logic Design Assignment No 03 Fall 2020 Solution & Discussion Due Date: 08-02-2021

 Digital Logic Design (CS302) Assignment # 03 Fall 2020 Total marks = 20 Deadline: 8 February 2021 Please carefully read the following instructions before attempting the assignment.   RULES FOR MARKING It should be clear that your assignment would not get any credit if: The assignment is submitted after the due date. The submitted assignment does not open or the file is corrupt. Strict action will be taken if the submitted solution is copied from any other student or the internet. You should concern the recommended books to clarify your concepts as handouts are not sufficient.  You are supposed to submit your assignment in Doc or Docx format. Any other formats like Scan Images, Pdf, Zip, Rar, Ppt and Bmp, etc will not be accepted.   Topic Covered: ·       PAL ·       PLA ·       GAL ·       ABEL NOTE No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignments in the last hour of the deadline. It is recommended to upload the solution file at least two days before its closing date.   If you people find any mistake or confusion in the assignment (Question statement), please consult with your instructor before the deadline. After the deadline, no queries will be entertained in this regard.   For any query, feel free to email at: cs302@vu.edu.pk

Questions No 01                                                         Marks (20)

You are provided with two figures. Figure 1 is a 10 x 5 Programmable Array Logic (PAL)circuit whereas Figure 2 is a 5 x 3 Programmable Logic Array (PLA) circuit. You are required to write An ABEL code/expression for both circuits.

PAL: 10 Inputs (I1, I2, I3, I4, I5, I6, I7, I8, I9, I10) & 5 Outputs (O1, O2, O3, O4, O5).

PLA: 5 Inputs (O1, O2, O3, O4, O5) & 3 Outputs (X, Y, Z).

Figure 1: Programmable Array Logic (PAL)

Figure 2: Programmable Logic Array (PLA)

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CS302-Assignment-3-Solution-Fall-2020

CS302-Assignment-3-Solution-Fall-2020.docx

CS302 Assignment 3 Solution Fall 2020

CS302 Assignment 3 Solution Fall 2020

CS302 Digital Logic Design Assignment solution No 03 Fall 2021

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CS302 Assignment 3 Solution Fall 2020 - 2021 ||Digital Logic Design||

CS302 Assignment 3 Fall 2020 solution idea:

SOLUTION:

PAL Circuit and Programming

A simplified PAL structure is shown where the AND array has been programmed to generate product terms which are added together by the OR array. Figure 1

Now we will find the the product terms (p)

P1 = i1`.i4.i7`.i8.i9.i10

P2= i2`.i5.i7.i9.i10`

P3= i1`.i2.i6`.i7`.i7.i9`.i10

P4=i1`.i3`.i5`.i7`.i9.i10

P5= i2`.i4`.i7.i9

P6= i1`.i3.i6`.i8`.i10`

Now we add together product terms

O=P1+P2+P3+P4+P5+P6

O=[ i1`.i4.i7`.i8.i9.i10+ i2`.i5.i7.i9.i10`+ i1`.i2.i6`.i7`.i7.i9`.i10+  i1`.i3`.i5`.i7`.i9.i10+ i2`.i4`.i7.i9+ i1`.i3.i6`.i8`.i10`]

NOW we write ABEL Expression

The NOT, AND, OR and XOR operations have special symbols in ABEL as shown

Logic Operation ABEL Symbol

NOT =   !

AND = &

OR   =   #

XOR =   \$

O=P1#P2#P3#P4#P5#P6;

O=!i1&i4&!i7&i8&i9&i10#!i2&i5&i7&i9&!i10#!i1&i2&!i6&!i7&i7&!i9&i10#!i1&!i3&!i5&!i7&i9&i10#!i2&!i4&i7&i9#!i1&i3&!i6&!i8&!i10;

Solution:

Programmable Logic Array as mentioned earlier has a programmable AND and OR arrays. A PLA can be programmed to implement any Sum-of-Product logic expressions,limited by the parameters of the PLA device.

NOW we generate product terms

P1=O2.O3.O5

P2=O1.O3.O4

P3=O1.O3.O5

P4=O2.O5

The first OR gate sums product terms P2 and P3 fuses for these product terms are seen to be intact. The second OR gate sums the product terms P2 and  P4 . The third OR gate sums the product terms P1, P3 and P4. The three sum-of-product terms are

Output X =P2+P3

Output y = P2+P4

Output z = P1+P3+P4

Now

Output x = O1.O3.O4+ O1.O3.O5

Output y= O1.O3.O4+ O2.O5

Output z= O2.O3.O5+ O1.O3.O5 + O2.O5

NOW we write ABEL Expression :

Output x= O1&O3&O4#O1&O3&O5

Output y=O1&O3&O4#O2&O5

Output z =O2&O3&O5#O1&O3&O5#O2&O5

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