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Total Marks = (10 + 10)
Part a. What will be the logic levels on the external FALCONA buses when each of the given FALCONA instruction is executing on the processor? Complete the table given. All numbers are in the decimal number.

Part b. Describe in your own words of how you completed the given table, instruction by instruction?

Instruction RTL equivalent Address Bus
<15..0> Data Bus
<15..0> MRead Mwrite
load r5, [11+r3]
addi r1,r2,30
jump [50]
store r3,[r4+18]
sub r3,r5,r6
shiftr r1,r6,4
mov r4,r1
jz r2, [-30]

This table shows the register map showing the contents of all the CPU registers.

Register Name Content
R[0] 492Fh
R[1] 0010h
R[2] 1D4Fh
R[3] 1123h
R[4] C4FEh
R[5] 2510h
R[6] 1456h
R[7] EF11h

This table contains a partial memory map showing the addresses and the corresponding data values.

Another important thing to note is that memory storage is big-endian.

Memory Address Memory Content
0020h 94h
0021h 2Fh
0022h 33h
0023h 12h
… …
C505h 07h
C506h 85h
C507h 44h
C508h 23h
C509h ACh
Memory Address Memory Content
C510h 69h
C511h F2h
C512h D9h
… …
1134h E4h
1135h 35h
1136h 51h
1137h 08h
1138h D3h
1139h F5h

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Replies to This Discussion

BUt table to as it is he ho ga na?????reply????????

registers k name theak kar len, 2nd instruction me

CS501+Assignment#2+Complete+Solution By M saqib khan

See the attached file 



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