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Assignment No. 02 Semester: Spring 2013 CS501: Advanced Computer Architecture,Total Marks: 20 Due Date: 06-05-13

Assignment No. 02
Semester: Spring 2013

CS501: Advanced Computer Architecture

                                                              Total Marks: 20

Due Date:  06-05-13

Instructions

Please read the following instructions carefully before assignment submission.

 

 

It should be clear that your assignment will not get any credit if:

 

  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is found to be copied from the internet.
  • The assignment is found to be copied from other student.
  • The assignment submitted is not according to required file format (.doc).

 

 

Objective

The objective of this assignment is:

 

  • To assess your overall understanding of Register Transfer Language and its notations.
  • To assess your overall understanding of binary encoding of Computer Instructions.
  • To assess your overall understanding of how data is being processed in Registers and memory.

 

 

 

Note:

 

  • The assignment should be in .doc format.
  • Assignment .02 covers lecture 6-10. You can also consult reference books for help.
  • Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

 

 

 

Question No 1:                                                 Marks 1+1+1+1+1=5

  Q. 1.                        Briefly explain the following Register Transfer Language (RTL) notations:

 

1)    R [1]           ß  R [2] + (-56)

2)   R[5] ←R[0] ©R[6]/R[3]

3)   R [4] ß  R [3] ~ R [1]

4)   IO[R [4]+1]ß  R[7]]

5)   M[R [1] +13]    ß   R [3]

 

 

Question No 2: Fill the given table by specifying binary encoded values against each instruction.                                                               

Marks 15

Instruction

Type

OP-Code

Ra

Rb

Rc

C1

C2

Addressing mode

RTL Description

Condition

PC status

ori r2, r4, 9

 

 

 

 

 

 

 

 

 

 

 


jnz r1, [27]

 

 

 

 

 

 

 

 

 

 

 

 

Out  7,R5(30)

 

 

 

 

 

 

 

 

 

 

 

Load R[6]+99]

 

 

 

 

 

 

 

 

 

 

 

Jmi  R3,[7]

 

 

 

 

 

 

 

 

 

 

 

 

Note: You may write N/A in a cell not relevant to any instruction.

 

 

                                              GOOD LUCK!

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Replies to This Discussion

4)    IO[R [4]+1]ß  R[7]]

value of the register R7 will move to the output device specified by the adding contents of the register R[4] and  const 1



5)    M[R [1] +13]    ß   R [3]

The value of ther r3 is being stored to the memory location that correspond to the location the sum of the constant 13 and the value stored in the r1.




jnz =10010(18)

jmi=10001(17)

bsff plz look at page98(hands out) 2nd table ma

 jnz jmi ki opcode ya ha

confrm kerin jo ap na table ma likhaya hain wo theek hain ya ya walya

Student's Message: Msg No. 584245
Subject: assignment problem in Q#2
Respected sir 
                       I think that in assignment 2, the question 2 have problems in instruction 3 and 4.Problem is that i think that in instruction 3 the value Out 7,R5(30) should be Out R7,R5(30) and in instruction 4 the value Load R[6]+99] should be as Load R1, R[6]+99].P;ease guide me that am i right and values should be change or all values in assignment are correct and we have to solve them as it.
Post Your Comments
Other Students' Comments: 0

Instructor's Reply:
Dear student 
                  We encourage your participation in MDBs. Out 7,R5(30) is actually Out R7,R5(30) R is a typing error but Load R[6]+99] is actually the Load R[6]+99] no typing error in it. 

Regards
Student's Message: Msg No. 584112
Subject: Assignment02
Dear Sir,
Which instruction set architecture should we use to solve the Question 2 of the assignment. Since different processors(SRC, Eagle, Falcon A) have different binary encoding for its instruction and they also have some common instructions. please clarify.
   
Post Your Comments
Other Students' Comments: 0

Instructor's Reply:
Dear student 
                  We encourage your participation in MDBs. You can use both Falcon-A or Falcon-E instruction architecture but it’s better to use Falcon-A architecture.

Regards

Assalam o alaekum

Here is the complete solution file of the assignment. No need to worry about making changes.

I hope you'll find a lot of helpful to it.

Please Pray for me

Rao Shahid

Attachments:

AllaH Bless U .. Ameen

light to hoti ni bhai ap jaldi upload kr dety  kia faida is naiki ka

sajid ali gud keep it up & thanks 

Note for All Members: You don’t need to go any other site for this assignment/GDB/Online Quiz solution, Because All discussed data of our members in this discussion are going from here to other sites. You can judge this at other sites yourself. So don’t waste your precious time with different links.

Assignment No. 02
Semester: Spring 2013

CS501: Advanced Computer Architecture

 

 

Mc110200890

 

Instructions

Please read the following instructions carefully before assignment submission.

 

 

It should be clear that your assignment will not get any credit if:

 

  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • The assignment is found to be copied from the internet.
  • The assignment is found to be copied from other student.
  • The assignment submitted is not according to required file format (.doc).

 

 

Objective

The objective of this assignment is:

 

  • To assess your overall understanding of Register Transfer Language and its notations.
  • To assess your overall understanding of binary encoding of Computer Instructions.
  • To assess your overall understanding of how data is being processed in Registers and memory.

 

 

 

Note:

 

  • The assignment should be in .doc format.
  • Assignment .02 covers lecture 6-10. You can also consult reference books for help.
  • Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

 

 

 

 

 

 

 

Assignment

 

 

Question No 1:                                                 Marks 1+1+1+1+1=5

  Q. 1.                        Briefly explain the following Register Transfer Language (RTL) notations:

 

1)  R [1]  ß  R [2] + (-56)

In this instruction the constant value -56 is being added to a register r2. the result is stored in dest. Register r1. this instruction has opcode 1

 

2)    R[5] ←R[0] ©R[6]/R[3]

 

In this inst the valaue of r6 register is divided and its second operand, by the number in the register r3 specified by the third operand, and assign the result to the dest register r5. opcode is 5.

3)    R [4] ß  R [3] ~ R [1]

 

In this instruction or inst is used to bit wise oring the contents of two registers named r3 and r1. the result is being stored in dest reg r4. opcode is 10

4)    IO[R [4]+1]ß  R[7]]

 

The out inst will move data from register r4+1 to the output device specified in the inst r7. its opcode is 25.

5)    M[R [1] +13]    ß   R [3]

 

In this inst the contents of reg r3 is being placed at the memory address calculated by the contents of register r1 plus constant 13.

 

 

 

 

 

 

 

Question No 2: Fill the given table by specifying binary encoded values against each instruction.                                                               

Marks 15

Instruction

Type

OP-Code

Ra

Rb

Rc

C1

C2

Addressing mode

RTL Description

Condition

PC status

ori r2, r4, 9

III

1011

R2

R4

 

9

 

Register

R2ß R4~9

 

 


jnz r1, [27]

 

II

10010

R1

 

 

 

27

relative

R[1]=0:PCß PC+27

IF R[1] not equal 0

PCß PC+27

Out  7,R5(30)

II

11001

R7

R5

 

30

 

Immediate

Cß R1;

IO[R7]ß C

 

 

Load R[6]+99]

III

11101

R6

 

 

99

 

Displacement

R6ß 99

 

 

Jmi  R3,[7]

II

10001

R3

 

 

 

7

Relative

R[3]=0:PCß PC+7

always

PCß PC+7

 

Note: You may write N/A in a cell not relevant to any instruction.

 

 

 

GOOD LUCK!

 

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