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# Assignment No. 3 (Due date: January 21, 2016.)

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Question#01:

You are required to do the following tasks from the SRC pipelined instructions given below:

1) Identify the hazard from the below given sequence of instructions (going through the pipelined version of SRC).

2) Identify the location of hazard from the below sequence of instructions.

3) Explain how above identified hazard can be resolved?

4) Resolve the hazard by using hazard-resolving mechanism.

SRC pipelined instructions:

200:  ld r7, r6, 65

204:  str r8, 43

208:  shl r4, 5

212:  shr r2, 5

220:  sub r1, r9, r5

Question#02:

Let us suppose, we have an I/O bus that can transfer 2 bytes of data in one bus cycle. If a system designer is going to attach the following two components to the I/O bus:

• Graphics card with a transfer rate of 20 Mbytes/sec
• Network card with a transfer rate of 40 Mbytes/sec

What will be the implications for the above scenario after adding two components (Graphic and Network card) to I/O bus?

Note: The maximum frequency of the bus is 20 MHz.

Our main purpose here discussion not just Solution

We are here with you hands in hands to facilitate your learning and do not appreciate the idea of copying or replicating solutions.

plzzzz any one give solution......

question no. 2.

one or both of these components will be operating at reduced bandwidth.

Idea For Question similar example  : 1

Consider the following sequence of the instructions giving through the pipelined version of SRC?

200:shl r6,r3,5

204:str r7,30

208:sub r2,r4,r5

216:id r7,48

Answer:- (Page 216) There is a data hazard between instruction three and four that can be resolved by using pipeline stalls or bubbles When using pipeline stalls, nop instructions are placed in between dependent instructions. The logic behind this scheme is that if opcode in stage 2 and 3 are both alu, and if ra in stage 3 is the same as rb or rc in stage 2, then a pause signal is issued to insert a bubble between stage 3 and 2. Similar logic is used for detecting hazards between stage 2 and 4 and stage 4 and 5.

idea for Second Question Similar Example:

Example # 1 Problem statement: Consider an I/O bus that can transfer 4 bytes of data in one bus cycle. Suppose that a designer is considering to attach the following two components to this bus:

Hard drive, with a transfer rate of 40 Mbytes/sec

Video card, with a transfer rate of 128 Mbytes/sec.

What will be the implications? Solution: The maximum frequency of the bus is 30 MHz10.

This means that the maximum bandwidth of this bus is 30 x 4 = 120 Mbytes/sec.

Now, the demand for bandwidth from these two components will be 128 + 40 =168 Mbytes/sec

which is more than the 120 10 These numbers correspond to an I/O bus that is relatively old.

Modern systems use much faster buses than this.

Mbytes/sec that the bus can provide. Thus, if the designer uses these two components with this bus, one or both of these components will be operating at reduced bandwidth.

Question 1 , from lecture 20 at 25:25 minuts.

dear some can help me for this one assignemnt

plzzzz any one give solution this assignment.........

e lwo

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thanks g

I can not hurt you...but my opinion is that your solution is not correct it is irrevelant and does not satisfiy....kindly think about it with great detail

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