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CS 501 Solved Subjective Questions for Mid Term Mega File

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CS 501 Solved Subjective Questions for Mid Term Mega File

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Question: 1

Write short answers to the following questions:

Differentiate between computer architecture and computer organization.

Answer:

Computer architecture:

Computer architecture refers to the attributes of a computer that are visible to a programmer, including

The instruction set

The number of bits used to represent various data types

I/O mechanisms

Memory addressing modes, etc.

 

Computer organization:

Computer organization refers to the operational units of a computer and their interconnections that realize the architectural specifications. These include

The control signals

Interfaces between the computer and its peripherals

Memory technology used, etc.

 

Why are MIPS (millions of instructions per second) a poor measure of a computer’s performance?

Answer:

MIPS is defined as

MIPS = IC/ (ET x 106)

This measure is not a very accurate basis for comparison of different processors. This is because of the architectural differences of the machines; some machines will require more instructions to perform the same job as compared to other machines.

 

What fields should be essentially specified in an instruction?

Answer:

Every instruction must contain encodings within it to specify the following four things, either explicitly or implicitly.

Type of operation

This is specified by the opcode.

Place to find source operands

The operand location may be explicitly specified, as in memory address or general register number, or it may be implicit within the opcode as in the accumulator in the accumulator based machines or on the stack of the stack based machines.

Place to store the results

The result location may need to be explicitly mentioned or it may be implicit in the opcode.

Source of the next instruction

In inline code the next instruction to execute is the next instruction in the sequence. In the instructions that alter the flow of the program statement execution the branch or jump address must be given as part of the current instruction.

 

Identify the instruction type and describe its respective instruction format of the following SRC instruction

                           Neg R3, R4

Answer:

Instruction Type                                Instruction Format

Modified Type D

 

Functionality: Negates (obtains 2’s complement) R4 and stores in R3. 2-address format and register addressing mode is used.

 

Define the Reverse Assembly.

           Answer:

Conversion of a machine language instruction required to find the equivalent assembly language instruction is known as Reverse Assembly.

 

Question: 2

Write the code to implement the following expression on 3, 2, 1, and 0 address    machines.

                        A=B x C – D x E

Answer:

 

3-Address

2-Address

1-Address

0-Address

mpy A,B,C

mpy X,D,E

sub A,A,X

load A,B

mpy A,C

load X,D

mpy X,E

sub A,X

lda B

mpy C

sta A

lda D

mpy E

sub A

sta A

push B

push C

mpy

pop A

push D

push E

mpy

push A

sub

pop A

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Question: 3

Consider a machine having a 100 MHz clock and three instruction types with following parameters. Now suppose that two different compilers generate code for the same program. The instruction count for each is given as follows:

 

IC in millions

Code from compiler 1

Code from compiler 2

Control

5

10

ALSU

2

1

Data Transfer

2

1

 

Instruction Type

CPI

Control

2

ALSU

3

Data Transfer

4

 

Compare the two codes according to MIPS and according to execution time.

Answer:

CPI = clock cycles for each type of instruction / IC,   and

ET = IC/ (MIPS * 106)

IC1= 5+2+2=9

CPI1= (5×2+2×3+4×2)/9=2.67,

MIPS1= 100×106/2.67×106           = 37.49995

ET1 = 9*106/ (37.49995*106) = 0.2368 Sec

IC2= 10+1+1=12

CPI2= (10×2+1×3+1×4)/12        = 2.25,

MIPS2= 100×106/2.25×106                = 44.44

ET2 = 12*106/ (44.44*106) = 0.2700 Sec

 

So code generated by compiler 2 has high MIPS rating.

 

Question: 4

Identify the addressing modes of the following instructions:

ldr R1, 14

ld R3, 6(R2)

Stop

str R7, 32

addi R3, R4, 25

nop

ori R2, R4, 56

lar R3, 48

Answer:

Relative addressing mode

Displacement addressing mode

None

Register relative addressing mode

Immediate addressing mode

None

Immediate addressing mode

Register relative addressing mode

 

Question: 5

Convert the following machine language instruction of SRC into the equivalent SRC assembly language instruction showing all the necessary steps.

       724E8000 h         

Answer:

1. Write the given hexadecimal instruction in binary form

724E8000 h ® 0111 0010 0100 1110 1000 0000 0000 0000 b

 

2. Examine the first five bits of the instruction, and pick the corresponding mnemonic from the SRC instruction set listing arranged according to ascending order of op-codes

01110 b ® 14 d ® sub ® subtract

3. Now we know that this instruction uses the type D format, the 5-bit field after the op-code field represents the destination and the two 5-bits fields after destination represents two source registers respectively, and that the remaining 12-bits in the instruction are unused.

 

0111 0010 0100 1110 1000 0000 0000 0000 b

op-code       ra               rb              rc                     12-bits     unused

 

    ¯        ¯        ¯         ¯                          ¯

  sub     R9      R7         R8       0 h=0 d

 

 

 

 

 

 

4. Therefore, the assembly language instruction is

 

 

                        Sub R9, R7, R8

 

 

Question: 6                                                                                                   

Explain the fetch operation of SRC using RTL.

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Answer:

The action performed for all the instructions before they are decoded is called ‘instruction interpretation’. Here, an example is that of starting the machine. If the machine is not already running (¬Run, or ‘not’ running), AND (&) it the condition start (Strt) becomes true, then Run bit (of the processor state) is set to 1 (i.e. true).

Instruction Fetch: = (

                          ! Run & Strt: Run ← 1                   ; instruction Fetch

              Run: (IR ← M [PC], PC ← PC + 4;      instruction_Execution));

The: = is the naming operator. The; operator is used to add comments in RTL. The, operator, specifies that the statements are to be executed simultaneously, (i.e. in a single clock pulse). The; operator is used to separate sequential statements. ← is an assignment operator. & is a logical AND, ~ is a logical OR, and! is the logical NOT. In the instruction interpretation phase of the fetch-execute cycle, if the machine is running (Run is true), the instruction register is loaded with the instruction at the location M [PC] (the program counter specifies the address of the memory at which the instruction to be executed is located). Simultaneously, the program counter is incremented by 4, so as to point to the next instruction, as shown in the example above. This completes the instruction interpretation.

 

Question: 7                                                                                       

Match the Instructions in column1 to their respective functional groups in column2.

 

      Column1

      Column2

subi

Shift

not

Data Transfer

asr

Logic

out

Control

iret

Arithmetic

Answer:

 

1→5

2→3

3→1

4→2

5→4

 

 

Question: 8                                                                                       

Draw the programmer’s view of FALCON-A.

Answer:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Question: 9                                                                                                   

      Identify the instruction types and their respective instruction formats of the following instructions of EAGLE.

Init   

     

Div          

Br          

Shiftl                

Mov 

Answer:

Instruction Type                                          Instruction Format

 

 a. Type Z                                                    

 

 b. Type Y

 

 c. Type W

 

 d. Type V

 

 e. Type X

 

 

 

 

Question: 10                                                                                                 

Identify the addressing modes of the following:

Which of the above given addressing modes are supported by FALCON-A and FALCON-E   processors?

M[R5]+d

M[R[4]+100]

[PC+50]

R4

[123]

M[R2]

Answer:

Auto-Increment

Displacement

PC-relative

Register

Direct

Register-indirect

 

    FALCON-A                                             FALCON-E

      Displacement                                            Displacement

      Register                                                     Register

      Register-indirect                      Direct

                                                                        Register-indirect   

 

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Question: 11                                                                                                 

Which factors are decided at processor design time?

Answer:

Following are the factors decided at the processor design time..

ISA Design

The first step in designing a processor is the specification of the instruction set of the processor.

Behavioral RTL Description

In this step, the behavior of the processor in response to the specific instructions is described in register transfer language.

Implementation of the Data Path

The data path design involves decisions like the placement and interconnection of various registers, the type of flip-flops to be used and the number and kind of the interconnection buses.

Structural RTL Description

In accordance with the chosen data path implementation, the structural RTL for every instruction is described in this step.

Control Unit Design

The control unit design is a rather tricky process as it involves timing and synchronization issues besides the usual combinational logic used in the data path design.

We can split the design procedure into two phases.

The data path design

The control unit design

 

Question: 12                                                                                                 

Give the structural RTL of the following SRC instructions.

ld

addi

st

shra

Answer:

                        A.

 

 

 

 

 

 

 

                        B.

 

 

 

 

 

 

 

                        C.

 

 

 

 

 

 

 

 

 

                        D.

 

 

 

 

 

 

 

 

 

Question: 13                                                                                                 

Briefly describe the control circuit for instruction fetch operation of SRC.

Answer:

Following is the list of the control signals that are needed to ensure the synchronized register transfers in the instruction fetch phase of SRC.

PCout: This control signal allows the contents of the Program Counter register to be written onto the internal processor bus.

LMAR: This signal enables write onto the memory address register (MAR), thus the value of PC that is on the bus, is copied into this register

INC4: It lets the PC value to be incremented by 4 in the ALSU, and result to be stored in C. Notice that the value of PC has been received by the ALSU as an operand. This control signal allows the constant 4 to be added to it.

The ALSU is assumed to include an INC4 function

LC: This enables the input to the register C for writing the incremented value of PC onto it.

During the time step T1, the following control signals are applied:

LMBR: This enables the “write” for the register MBR. When this signal is activated, whatever value is on the bus, can be written into the MBR.

MRead: Allow memory word to be gated from the external CPU data bus into the MBR.

MARout: This signal enables the tri-state buffers at the output of MAR.

Cout: This will enable writing of the contents of register C onto the processor’s internal data bus.

LPC: This will enable the input to the PC for receiving a value that is currently on the internal processor bus. Thus the PC will receive an incremented value.

At the final time step, T2, of the instruction fetch phase, the following control signals are issued:

MBRout: To enable the tri-state buffers with the MBR.

LIR: To allow the IR read the value from the internal bus. Thus the instruction stored in the MBR is read into the Instruction Register (IR).

           

Question: 14                                                                                                 

What is the purpose of sign-extension in case of SRC?

Answer:

When we copy constant values to registers that are 32 bits wide, we need to sign extend the values first. This is done to preserve the sign of the constant. These values are in the 2’s complement form, and to sign-extend these values, we need to copy the most significant bit to all the additional bits in the register.

 

Question: 15                                                                                                 

Write the structural RTL of the brlzr ra, rb, rc instruction of SRC with appropriate control signals.

Answer:

 

 

 

 

 

 

Question: 16

Classify the following general instructions on the basis of functionality.

 

Load

Add

Halt

Shift

Jump

 

Answer

 

 

    Load                                                    Data storage instructions

                       

    Add                                                 Data processing instructions

 

    Shift                                                              Data processing instructions

           

          Jump                                                      Program flow control instructions

 

          Halt                                                       Miscellaneous Instructions

 

Question # 17

Convert the following machine language instruction of SRC into the equivalent SRC assembly language instruction showing all the necessary steps.

           724D8000 h

 

Write the given hexadecimal instruction in binary form

724D8000 h  ® 0111 0010 0100 1101 1000 0000 0000 0000 b

 

 

 Examine the first five bits of the instruction, and pick the corresponding mnemonic from the SRC instruction set listing arranged according to ascending order of op-codes

 

01110 b ® 14 d ® sub ® 2’s Compliment subtraction

 

Now we know that this instruction uses the Type D format, the three 5-bit fields after the op-code field represent the one destination and the two source registers respectively, and that the remaining 12-bits in the instruction unused bits.

 

 

      0111 0010 0100 1101 1000 0000 0000 0000 b

      op-code ra field  rb field   rc field            12-bit unused field

          ¯        ¯        ¯            ¯              ¯

        Sub     R9      R6          R24     

 

 

 

 

 

 

4. Therefore, the assembly language instruction is

 

 

                        Sub R9, R6, R24

 

Question: 18                                                                                                      

 Consider two programs having three types of instructions given as follows

 

Number of ...

Program 1

Program 2

data transfer instructions

3

7

control instructions

1

2

ALSU Instructions

4

5

 

Instruction Type

CPI

Control

3

ALSU

2

Data Transfer

6

 

Compare both the programs for the following parameters:

 Instruction count

 Speed of execution

 

Answer

 

IC1= 3+1+4=8

IC2= 7+2+5=14

 

(ii)

 

ET1= 3×6+1×3+4×2 = 18+3+8   = 29sec

ET2= 7×6+2×3+5×2 = 42+6+10 = 58sec

Question: 19                                                                                                 

 Two implementations of the same instruction set architecture:

à   Machine (A) has a clock cycle time of 15 ns, and a CPI of 2.37.

à   Machine (B) has a clock cycle time of 17 ns, and a CPI of 1.89.

Which machine is faster (for the same program), and by how much?

 

Answer

 

Assuming

IC is same for both machines so it will remain constant i.e. =X

 

 

ET=IC x CPI x T

 

ETA=ICAx 2.37 x 15 x 10-9        =      X x 35.55 x 10-9   =    35.55 nsec

ETB=ICB x 1.89 x 17 x 10-9        = X x 32.13 x 10-9      = 32.13 nsec

 

Hence machine B runs faster.    It is 35.55/32.13 = 1.1 times faster than machine A.

 

Question: 20

What is the difference between “branch” and “branch link” instructions of SRC?

Answer:

 

 

                      Br                                                                               brl

Branch instruction branches to address   Branch link branches to address in Rb     

In Rb depending on the condition in rc.                                depending on condition in rc.                                                                                                          

                                                                          Additionally, it copies the PC into ra 

                                                                                              before branching.

 

Question: 21

What is meant by “disjoint” statements?

 

Answer:

Disjoint statements show that only one of the statements is executed, depending on the condition met and then the instruction fetch statement (iF) is invoked again at the end of the list of concurrent statements.

 

Question: 22

Find the bandwidth of a memory system that has a latency of 30ns, a pre charge time of 10ns and transfers 3 bytes of data per access

Answer:

 

Time between two memory references

=latency + pre charge time

= 30 ns+ 10ns

= 40ns

Throughput = 1/40ns

=2.5x107

Bandwidth   = 3x 2.5x107

= 7.5x107

 

 

Question: 22

 

Define an I/O port. Which functions are performed by it?

Answer

 

An interface that can be used to connect the microcomputer bus to peripheral devices is called an I/O Port. I/O ports serve the following three purposes:

Buffering (i.e., holding temporarily) the data to and from the computer bus.

Holding control information that dictates how a transfer is to be conducted.

Holding status information so that the processor can monitor the activity of the interface and its associated I/O element.

Question # 23

 

Specify the condition for the branch instruction and the status of the PC after the branch instruction executes with a true branch condition.

 

Instruction

Condition

PC status

Jump[21]

Always

PC← PC+21

Jnz r5,[17]

If R[5] ≠ 0

PC← PC+17

Jz r2,[29]

If R[2] = = 0

PC← PC+29

Jpl r3,[17]

If R[3] ≥0

PC← PC+17

Jmi r7,[26]

If R[7] < 0

PC← PC+26

 

Question # 24

Identify the addressing modes and Register Transfer Language (RTL) description (meaning) for the given Falcon-A instructions

Answer

 

Instruction

Addressing Mode

RTL description(meaning)

Load r2,[r5+13]

Displacement

R[2] ← M[R[5] +13]

Jnz r4,[24]

Relative

(If R[4] ≠ 0): PC← PC+24

Shiftl r4,r5,6

Immediate

Shift r5 left 6 times and store in r4

Add r2,r3,r4

Register

R[2] ← R[3] + R[4]

Subi r4,r5,7

Immediate

R[4] ← R[5] -7

 

 

 

Question: 25

Write short answers to the following questions:

What is meant by the ‘stored program concept’? What is the alternative to this style of computing?

Answer:
It states that the program is stored with data in computer’s memory, and the computer is able to manipulate it as data. An alternative to this style of computing was machines programmed with plug-boards, punched paper tape, or some other external mechanical means. Loading a program meant plugging in a patch board or running a paper tape through a reader.    

Question # 26

What are the different ways to enlist an instruction set architecture?

Answer:

There are three ways to list instructions in an instruction set of a computer:

by function categories

by an alphabetic ordering of mnemonics

by an ascending order of op-codes

Question # 27

What are the functions provided by the debugger during the development of assembly language programs?

Answer:
Debuggers provide functionality such as

The display and altering of the contents of memory, CPU registers and flags

Disassembly of machine code (translating the machine code back to assembly language)

Single stepping and breakpoints that allow the examination of the status of the program and registers at desired points during execution.

Question # 28

 

What are the responsibilities of a computer architect?

Answer:

The computer architect performs the following tasks:

Designs the ISA for optimum programming utility as well as for optimum performance of implementation

Designs the hardware for best implementation of instructions that are made available in the ISA to the programmer

Uses performance measurement tools, such as benchmark programs, to verify that the performance objectives are met by the machine designed

Balances performance of building blocks such as CPU, memory, I/O devices, and interconnections

Strives to meet performance goals at the lowest possible cost

Question # 29

State the advantages of stack-based machines.

Answer:

In stack based machine no operand addresses need to be specified during an arithmetic operation so this is known as 0-address machine. Implicit operands like a stack reduces the instruction size, as they need not be coded into the instruction and thus this reduces the code density (which implies how many instructions can be encoded in a given number of bits).

Question # 30

Compare and contrast the register-memory and memory-memory machines. www.vustudents.ning.com

 

Answer:

Register-memory machines

Advantages
Register-memory operations use one memory operand out of a total of two operands. The advantages of this instruction format are

Operands in the memory can be accessed without having to load these first through a separate load instruction

Encoding is easy due to the elimination of the need of loading operands into registers first

Instruction bit usage is relatively better, as more instructions are provided per fixed number of bits

Disadvantages

Operands are not equivalent since one operand may have two functions (both source operand and destination operand), and the source operand may be destroyed

Different size encoding for memory and registers may restrict the number of registers

Depending on the location of the operand in the memory, the number of clock cycles per instruction is different. Operand fetch from memory is slow as compared to operand fetch from CPU registers

Memory-Memory Machines         

Advantages

The memory-memory instructions are the most compact instruction where encoding wastage is minimal.

As operands are fetched from and stored in the memory directly, no CPU registers are wasted for temporary storage  

Disadvantages

The instruction size is not fixed; the large variation in instruction sizes makes decoding complex

The cycles per instruction execution also vary from instruction to instruction

Memory accesses are generally slow, so too many references cause performance degradation

 

 

Question # 31

 

What is the advantage of pre-fetching and speculative execution?

Answer:

Pre-fetching and speculative execution techniques are used with a pipelined architecture. Instruction pipelining means having multiple instructions in different stages of execution. As new instructions are issued before the preceding instructions have completed execution, the processor will not know in case of a conditional branch instruction, whether the condition will be met and the branch will be taken or not. But instead of waiting for this information to be available, the branch can be “speculated” as taken or not taken, and the instructions can be issued. Later if the speculation is found to be wrong, the results can be discarded and actual target instructions can be issued.. These techniques help improve the performance of processors.

 

Question # 32

 

What are the advantages of using MFLOPS as performance metric?

Answer:

MFLOPS has two advantages:

Floating point operations are complex, and therefore, provide a better picture of the hardware capabilities on which they are run

Overheads (operand fetch from memory, result storage to the memory, etc.) are effectively lumped with the floating point operations they support

Question # 33

List some programs included in SPEC benchmark suit

Answer:

The standard SPEC benchmark suite includes:

A compiler

A Boolean minimization program

A spreadsheet program

A number of other programs that stress arithmetic processing speed

Question # 34

 

Define ‘Cross Assembler’.

Answer:

An “assembler” that runs on one processor and translates an assembly language program into the machine language of another processor is called a “cross assembler”

 

 

 

Question: 35

Arrange the following digital design levels from the most abstract level to the         lowest physical level:

Register transfer level

Mask level

Processor-memory-switch level

Instruction set level

Circuit level

Logic design level

Answer:

 

Processor-memory-switch level

Instruction set level

Register transfer level

Logic design level

Circuit level

Mask level

Question: 19                                                                                                 

 Two implementations of the same instruction set architecture:

à   Machine (A) has a clock cycle time of 15 ns, and a CPI of 2.37.

à   Machine (B) has a clock cycle time of 17 ns, and a CPI of 1.89.

Which machine is faster (for the same program), and by how much?

 

Answer

 

Assuming

IC is same for both machines so it will remain constant i.e. =X

 

 

ET=IC x CPI x T

 

ETA=ICAx 2.37 x 15 x 10-9        =      X x 35.55 x 10-9   =    35.55 nsec

ETB=ICB x 1.89 x 17 x 10-9        = X x 32.13 x 10-9      = 32.13 nsec

 

Hence machine B runs faster.    It is 35.55/32.13 = 1.1 times faster than machine A.

 

Question: 20

What is the difference between “branch” and “branch link” instructions of SRC?

Answer:

 

 

                      Br                                                                               brl

Branch instruction branches to address   Branch link branches to address in Rb     

In Rb depending on the condition in rc.                                depending on condition in rc.                                                                                                          

                                                                          Additionally, it copies the PC into ra 

                                                                                              before branching.

 

Question: 21

What is meant by “disjoint” statements?

 

Answer:

Disjoint statements show that only one of the statements is executed, depending on the condition met and then the instruction fetch statement (iF) is invoked again at the end of the list of concurrent statements.

 

Question: 22

Find the bandwidth of a memory system that has a latency of 30ns, a pre charge time of 10ns and transfers 3 bytes of data per access

Answer:

 

Time between two memory references

=latency + pre charge time

= 30 ns+ 10ns

= 40ns

Throughput = 1/40ns

=2.5x107

Bandwidth   = 3x 2.5x107

= 7.5x107

 

 

Question: 22

 

Define an I/O port. Which functions are performed by it?

Answer

 

An interface that can be used to connect the microcomputer bus to peripheral devices is called an I/O Port. I/O ports serve the following three purposes:

Buffering (i.e., holding temporarily) the data to and from the computer bus.

Holding control information that dictates how a transfer is to be conducted.

Holding status information so that the processor can monitor the activity of the interface and its associated I/O element.

Question # 23

 

Specify the condition for the branch instruction and the status of the PC after the branch instruction executes with a true branch condition.

 

Instruction

Condition

PC status

Jump[21]

Always

PC← PC+21

Jnz r5,[17]

If R[5] ≠ 0

PC← PC+17

Jz r2,[29]

If R[2] = = 0

PC← PC+29

Jpl r3,[17]

If R[3] ≥0

PC← PC+17

Jmi r7,[26]

If R[7] < 0

PC← PC+26

 

Question # 24

Identify the addressing modes and Register Transfer Language (RTL) description (meaning) for the given Falcon-A instructions

Answer

 

Instruction

Addressing Mode

RTL description(meaning)

Load r2,[r5+13]

Displacement

R[2] ← M[R[5] +13]

Jnz r4,[24]

Relative

(If R[4] ≠ 0): PC← PC+24

Shiftl r4,r5,6

Immediate

Shift r5 left 6 times and store in r4

Add r2,r3,r4

Register

R[2] ← R[3] + R[4]

Subi r4,r5,7

Immediate

R[4] ← R[5] -7

 

 

 

Question: 25

Write short answers to the following questions:

What is meant by the ‘stored program concept’? What is the alternative to this style of computing?

Answer:
It states that the program is stored with data in computer’s memory, and the computer is able to manipulate it as data. An alternative to this style of computing was machines programmed with plug-boards, punched paper tape, or some other external mechanical means. Loading a program meant plugging in a patch board or running a paper tape through a reader.    

Question # 26

What are the different ways to enlist an instruction set architecture?

Answer:

There are three ways to list instructions in an instruction set of a computer:

by function categories

by an alphabetic ordering of mnemonics

by an ascending order of op-codes

Question # 27

What are the functions provided by the debugger during the development of assembly language programs?

Answer:
Debuggers provide functionality such as

The display and altering of the contents of memory, CPU registers and flags

Disassembly of machine code (translating the machine code back to assembly language)

Single stepping and breakpoints that allow the examination of the status of the program and registers at desired points during execution.

Question # 28

 

What are the responsibilities of a computer architect?

Answer:

The computer architect performs the following tasks:

Designs the ISA for optimum programming utility as well as for optimum performance of implementation

Designs the hardware for best implementation of instructions that are made available in the ISA to the programmer

Uses performance measurement tools, such as benchmark programs, to verify that the performance objectives are met by the machine designed

Balances performance of building blocks such as CPU, memory, I/O devices, and interconnections

Strives to meet performance goals at the lowest possible cost

Question # 29

State the advantages of stack-based machines.

Answer:

In stack based machine no operand addresses need to be specified during an arithmetic operation so this is known as 0-address machine. Implicit operands like a stack reduces the instruction size, as they need not be coded into the instruction and thus this reduces the code density (which implies how many instructions can be encoded in a given number of bits).

Question # 30

Compare and contrast the register-memory and memory-memory machines. www.vustudents.ning.com

 

Answer:

Register-memory machines

Advantages
Register-memory operations use one memory operand out of a total of two operands. The advantages of this instruction format are

Operands in the memory can be accessed without having to load these first through a separate load instruction

Encoding is easy due to the elimination of the need of loading operands into registers first

Instruction bit usage is relatively better, as more instructions are provided per fixed number of bits

Disadvantages

Operands are not equivalent since one operand may have two functions (both source operand and destination operand), and the source operand may be destroyed

Different size encoding for memory and registers may restrict the number of registers

Depending on the location of the operand in the memory, the number of clock cycles per instruction is different. Operand fetch from memory is slow as compared to operand fetch from CPU registers

Memory-Memory Machines         

Advantages

The memory-memory instructions are the most compact instruction where encoding wastage is minimal.

As operands are fetched from and stored in the memory directly, no CPU registers are wasted for temporary storage  

Disadvantages

The instruction size is not fixed; the large variation in instruction sizes makes decoding complex

The cycles per instruction execution also vary from instruction to instruction

Memory accesses are generally slow, so too many references cause performance degradation

 

 

Question # 31

 

What is the advantage of pre-fetching and speculative execution?

Answer:

Pre-fetching and speculative execution techniques are used with a pipelined architecture. Instruction pipelining means having multiple instructions in different stages of execution. As new instructions are issued before the preceding instructions have completed execution, the processor will not know in case of a conditional branch instruction, whether the condition will be met and the branch will be taken or not. But instead of waiting for this information to be available, the branch can be “speculated” as taken or not taken, and the instructions can be issued. Later if the speculation is found to be wrong, the results can be discarded and actual target instructions can be issued.. These techniques help improve the performance of processors.

 

Question # 32

 

What are the advantages of using MFLOPS as performance metric?

Answer:

MFLOPS has two advantages:

Floating point operations are complex, and therefore, provide a better picture of the hardware capabilities on which they are run

Overheads (operand fetch from memory, result storage to the memory, etc.) are effectively lumped with the floating point operations they support

Question # 33

List some programs included in SPEC benchmark suit

Answer:

The standard SPEC benchmark suite includes:

A compiler

A Boolean minimization program

A spreadsheet program

A number of other programs that stress arithmetic processing speed

Question # 34

 

Define ‘Cross Assembler’.

Answer:

An “assembler” that runs on one processor and translates an assembly language program into the machine language of another processor is called a “cross assembler”

 

 

 

Question: 35

Arrange the following digital design levels from the most abstract level to the         lowest physical level:

Register transfer level

Mask level

Processor-memory-switch level

Instruction set level

Circuit level

Logic design level

Answer:

 

Processor-memory-switch level

Instruction set level

Register transfer level

Logic design level

Circuit level

Mask level

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