We have been working very hard since 2009 to facilitate in learning Read More. We can't keep up without your support. Donate.

www.bit.ly/vucodes

+ Link For Assignments, GDBs & Online Quizzes Solution

www.bit.ly/papersvu

+ Link For Past Papers, Solved MCQs, Short Notes & More

CS 501 Solved Subjective Questions for Mid Term Mega File

See the attached file please


+ http://bit.ly/vucodes (Link for Assignments, GDBs & Online Quizzes Solution)

+ http://bit.ly/papersvu (Link for Past Papers, Solved MCQs, Short Notes & More)

+ Click Here to Search (Looking For something at vustudents.ning.com?)

+ Click Here To Join (Our facebook study Group)


Views: 4046

Attachments:

Replies to This Discussion

Note: (This is Featured Discussion)

For Important Helping Material related to this subject (Solved MCQs, Short Notes, Solved past Papers, E-Books, FAQ,Short Questions Answers & more). You must view all the featured Discussion in this subject group.

For how you can view all the Featured discussions click on the Back to Subject Name Discussions link below the title of this Discussion & then under featured Discussion corner click on the view all link.

CS501 MIDTERM QUIZ SOLVED

Attachments:

CS501_Subjective_Objective_Solved

Attachments:

Question # 1

 

In which of the following addressing modes, the operand does not specify an address but it is the actual data to be used.

 

Direct

 

Indirect

 

Immediate

 

Relative

 

Question # 2

 

Which one of the following registers holds the address of the next instruction to be executed?

 

 

Accumulator

 

Address Mask

 

Instruction Register

 

Program Counter

 

 

Question # 3

 

In which of the following techniques, the time a process spends waiting for instructions to be fetched from memory is minimized?

 

Prefecting

 

Pipelining

 

Superscalar operation

 

Speedup

 

Question # 4

 

The external interface of FALCON-A consists of a         address bus.

 

 

8-bit

 

16-bit

 

24-bit

 

32-bit

 

Question # 5 

 

Which one of the following is the memory organization of EAGLE processor?

 

2^8*8 bits

 

2^16*8 bits

 

2^32*8 bits

 

2^64*8 bits

 

Question # 7

 

The External interface of FALCON-A  consists of a         address bus and a         data bus.

 

 

8bit, 8bit

 

16-bit,16-bit

 

16-bit,24-bit

 

16-bit, 32-bit

 

Question # 8

 

Computer system performance is usually measured by the         

 

Time to execute a program or program mix

 

The speed with which it executes programs

 

Processor’s utilization in solving the problems

 

Instructions that can be carried out simultaneously

 

 

Question # 9

 

Which one of the following registers holds the instruction that is being executed?

 

Accumulator

 

Address Mask

Instruction Register

 

Program Counter

 

 

Question # 10

Matorola  MC68000 is an example of       microprocessor.

 

Cisc

 

Risc

 

SRC



dentify the opcode, destination register (DR), source registers (SA and SB i/e source register A and source register B) from the following example. ADD R1, R2, R3
Select correct option:

Opcode= R1, DR=ADD, SA=R2, SB=R3
Opcode= ADD, DR=R1, SA=R2, SB=R3
Opcode= R2, DR=ADD, SA=R1, SB=R3
Opcode= ADD, DR=R3, SA=R2, SB=R1

Which type of instructions help in changing the flow of the program as and when required?
Select correct option:

Arithmetic
Control
Data transfer
Floating point

Almost every commercial computer has its own particular ---------- language
Select correct option:

3GL
English language
Higher level language
assembly language

Which one of the following is a binary cell capable of storing one bit of information?
Select correct option:

Decoder
Flip-flop
Multiplexer
Diplexer

Which statement(s)from the following is/are correct about Reduced Instruction Set Computer (RISC) architectures.

(i)                   The typical RISC machine instruction set is small, and is usually a subject of a CISC instruction set.

(ii)                 (ii) No arithmetic or logical instruction can refer to the memory directly.

(iii)                (iii) A comparatively large number of user registers are available.

(iv)                (iv) Instructions can be easily decoded through hard-wired control units.
Select correct option:

(i) and (iii) only
(i), (iii) and (iv)
(i), (ii) and (iii) only
(i),(ii),(iii) and (iv)

What is the instruction length of the FALCON-E processor?
Select correct option:

8 bits
16 bits
32 bits
64 bits

Which one of the following are the code size and the Number of memory bytes respectively for a 3-address instruction?
Select correct option:

0 bytes, 10 bytes
4 bytes, 7 bytes
7 bytes, 16 bytes
10 bytes, 19 bytes

 

The CPU includes three types of instructions, which have different operands and will need different representations. Which one of the instructions requires two source registers?

Select correct option:

Jump and branch format instructions
Immediate format instructions
Register format instructions
All of the above

Which one of the following are the code size and the Number of memory bytes respectively for a 2-address instruction?
Select correct option:

4 bytes, 7 bytes
7 bytes, 16 bytes
10 bytes, 19 bytes
13 bytes, 22 bytes

 

Nadia: P: R3 <- R5 MAR <- IR These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?
Select correct option:

Parentheses ()
Arrow <-
Colon :
Comma ,

In which of the following instructions the data move between a register in the processor and a memory location (or another register) and are also called data movement?
Select correct option:

Arithmetic/logic
Load/store
Test/branch
None of the given


In which one of the following addressing modes, the operand does not specify an address but it is the actual data to be used.
Select correct option:

Direct
Indirect
Immediate
Relative


Which one of the following portions of an instruction represents the operation to be performed?
Select correct option:

Address
Instruction code
Opcode
Operand


Subjective CS501- Computer Architecture

Question: - Write down two processors name of superscalar architecture.  (PIRLCM)

Answer:  A scalar processor that can issue multiple instructions simultaneously is said to be superscalar. Name of some superscalar processors are: PowerPC 601, Intel P6, DEC Alpha 21164

 

Question: - How exception may be generated write the difference between external and internal exceptions?

Answer: Anything that interrupts the normal flow of execution of instructions in the processor is called an exception. Exceptions may be generated by an external or internal event such as a mouse click or an attempt to divide by zero etc.

External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock)

 

 

 Question: - What are the pipeline problems? Describe each briefly…. 5marks

Data dependence

This refers to the situation when an instruction in one stage of the pipeline uses the results of an instruction in the previous stage.

 Data forwarding

When using data forwarding, special hardware is added to the processor, which allows

the results of a particular pipeline stage to be transferred directly to another stage in the

pipeline where they are required.

Branch delay

Branches can cause problems for pipelined processors. It is difficult to predict whether a branch will be taken or not before the branch condition is tested.

Load delay

Another problem surfaces when a value is loaded into a register and then immediately used in the next operation.

 

Question: Why are MIPS (millions of instructions per second) a poor measure of a computers performance?

Answer: MIPS is defined as MIPS = IC/ (ET x 106)

This measure is not a very accurate basis for comparison of different processors. This is because of the architectural differences of the machines; some machines will require more instructions to perform the same job as compared to other machines.

 

Question: Define the Reverse Assembly.

Answer: Conversion of a machine language instruction required to find the equivalent assembly language instruction is known as Reverse Assembly.

 

Question: What is the purpose of sign-extension in case of SRC?

Answer: When we copy constant values to registers that are 32 bits the values first. This is done to preserve the sign of the constant.2‟s complement form, and to sign-extend these values, we significant bit to all the additional bits in the register.

 

Question: What is meant by “disjoint” statements?

Answer: Disjoint statements show that only one of the statements is executed, depending on the condition met and then the instruction fetch statement (iF) is invoked again at the end of the list of concurrent statements.

 

Question: What are the different ways to enlist an instruction set architecture?

Answer: There are three ways to list instructions in an instruction set of a computer:

by function categories ,  by an alphabetic ordering of mnemonics ,  by an ascending order of op-codes

 

 

Question:  List some programs included in SPEC benchmark suit

Answer: The standard SPEC benchmark suite includes: A compiler, A Boolean minimization program

A spreadsheet program, A number of other programs that stress arithmetic processing speed

 

Question: Define „Cross Assembler‟.

Answer: An “assembler” that runs on one processor and translates an assembly language into the machine language of another processor is called a “cross assembler”

 

Question: Define the “addressing mode” and briefly describe the common addressing modes.

Answer: An addressing mode is the method by which architectures specify the address of an object they will access. The object may be a constant, a register or a location in memory. Common addressing modes are: Immediate, Register, Direct, Register indirect, Displacement. 

>>>>>>>>> Objective Type – CS501 – Computer Architecture

What is the instruction length of the FALCON-E processor? Select correct option: 

8 bits               16 bits                         32 bits             64 bits


Which one of the following circuit design levels is called the gate level? Select correct option:
Logic Design Level  Circuit Level    Mask Level      None of the given

 

What does the word ‘D’ in the ‘D-flip-Flop’ stands for?Select correct option:
Data                Digital             Dynamic          Double


The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
Add R3, 56                  lar R3, 56        ldr R3, 56        str R3, 56


Which one of the following registers holds the instruction that is being executed?
Accumulator                Address Mask             Instruction Register Program Counter


For any of the instructions that are a part of the instruction set of the SRC, there are certain ____________ required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
Registers        Control signals                     Memory           None of the given


The external interface of FALCON-A consists of a ________ data bus.
8-bit                 16-bit              24-bit               32-bit

__________ enable the input to the PC for receiving a value that is currently on the internal processor bus.
LPC                 INC4                LC       Cout

Which one of the following register(s) that is/are programmer invisible and is/are required to hold an operand or result value while the bus is busy transmitting some other value?
Instruction Register                 Memory address register
Memory Buffer Register                      Registers A and C

-------------- performs the data operations as commanded by the program instructions.
Select correct option:
Control                                    Data path        Structural RTL                      Timing

 

What is the size of the memory space that is available to FALCON-A processor?
2^8 bytes    2^16 bytes    2^32 bytes    2^64 bytes

How can we refer to an instruction register (IR), of 16 bits (numbered 0 to 15) using RTL?
IR<16..0>     IR<15..0>      IR<16..1>    IR<15..1>

What is the working of Processor Status Word (PSW)?
To hold the current status of the processor.  To hold the address of the current process
 
what does the instruction “ldr R3, 58” of SRC do?
It will load the register R3 with the contents of the memory location M [PC+58]
It will load the register R3 with the relative address itself (PC+58).
It will store the register R3 contents to the memory location M [PC+58]
No operation

 
What is the instruction length of the FALCON-E processor?
8 bits  16 bits  32 bits   64 bits

Which one of the following portions of an instruction represents the operation to be performed?
Address    Instruction code   Opcode    Operand


For the __________ type instructions, we require a register to hold the data that is to be loaded from the memory, or stored back to the memory
Jump               Control                        load/store      None of the given

Which one of the following is the highest level of abstraction in digital design in which the computer architect views the system for the description of system components and their interconnections?
Processor-Memory-Switch level (PMS level)      Instruction Set Level
Register Transfer Level                                              None of the given

Identify the opcode, destination register (DR), source registers (SA and SB i/e source register A and source register B) from the following example. ADD R1, R2, R3
Opcode= R1, DR=ADD, SA=R2, SB=R3                  Opcode= ADD, DR=R1, SA=R2, SB=R3
Opcode= R2, DR=ADD, SA=R1, SB=R3                  Opcode= ADD, DR=R3, SA=R2, SB=R1


Which one of the following circuit design levels is called the gate level?
Logic Design Level Circuit Level    Mask Level      None of the given

The CPU includes three types of instructions, which have different operands and will need different representations. Which one of the instructions requires two source registers?
Jump and branch format instructions             Immediate format instructions
Register format instructions                       All of the above

P: R3 <- R5 MAR <- IR These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?
Parentheses ()                        Arrow<-                       Colon :             Comma ,

In which of the following instructions the data move between a register in the processor and a memory location (or another register) and are also called data movement?
Arithmetic/logic                       Load/store     Test/branch     None of the given

What does the word ‘D’ in the ‘D-flip-Flop’ stands for?
Data                Digital             Dynamic                      Double

The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
Add R3, 56      lar R3, 56        ldr R3, 56        str R3, 56

What is the instruction length of the FALCON-E processor?
8 bits               16 bits             32 bits             64 bits

Which one of the following are the code size and the Number of memory bytes respectively for a 2-address instruction?
4 bytes, 7 bytes                       7 bytes, 16 bytes                   10 bytes, 19 bytes       13 bytes, 22 bytes

Which one of the following portions of an instruction represents the operation to be performed?
Address                       Instruction code                      Opcode                      Operand

Which operator is used to ‘name’ registers, or part of registers, in the Register Transfer Language?
:=         &          %         ©


What is the size of the memory space that is available to FALCON-A processor?
2^8 bytes         2^16 bytes     2^32 bytes       2^64 bytes

An “assembler” that runs on one processor and translates an assembly language program written for another processor into the machine language of the other processor is called a ----------------
compiler                      cross assembler                   debugger         linker

Which instruction is used to store register to memory using relative address?
ld instruction                ldr instruction  lar instruction            str instruction

What does the instruction “ldr R3, 58” of SRC do?
It will load the register R3 with the contents of the memory location M [PC+58]
It will load the register R3 with the relative address itself (PC+58).
It will store the register R3 contents to the memory location M [PC+58]
No operation

Which of the following can be defined as an address of the operand in a computer type instruction or the target address in a branch type instruction?
Base address Binary address            Effective address                 All of the given

How can we refer to an instruction register (IR), of 16 bits (numbered 0 to 15) using RTL?
IR<16..0>        IR<15..0>        IR<16..1>        IR<15..1>

What functionality is performed by the instruction “str R8, 34” of SRC?
It will load the register R8 with the contents of the memory location M [PC+34]
It will load the register R8 with the relative address itself (PC+34).
It will store the register R8 contents to the memory location M [PC+34]
No operation

Which type of instructions help in changing the flow of the program as and when required?
Arithmetic        Control                       Data transfer   Floating point

Whic of the following statements is/are true about RISC processors’ claimed advantages over CISC processors? (a) Keeping regularly accessed variables in registers as opposed to keeping them in memory facilitates faster execution. (b) RISC CPUs outperform CISC CPU’s in procedural programming environments. (c) Instruction pipelining has helped RISC CPU’s to attain a target of 1 cycle per instruction. (d) It is easier to maintain the “family concept” in RISC CPUs.
(a), (b) &(c)
(b), (c) & (e)
(c), (d) & (e)
(a), (c) & (d)

Which one of the following is the highest level of abstraction in digital design in which the computer architect views the system for the description of system components and their interconnections?
Processor-Memory-Switch level (PMS level)      Instruction Set Level  Register Transfer Level          None of the given

Which one of the following is/are the features of Register Transfer Language? a) It is a symbolic language b) It is describing the internal organization of digital computers c) It is an elementary operation performed (during one clock pulse), on the information
(b) only                       (a) & (b)                       only(a) ,(b) & (d)                      (b),(c) & (d)

In which of the following instructions the data move between a register in the processor and a memory location (or another register) and are also called data movement?:
Arithmetic/logic                       Load/store                 Test/branch     None of the given

Motorola MC68000 is an example of ---------microprocessor.
CISC   RISC   SRC    FALCON

Which one of the following registers holds the instruction that is being executed?
Accumulator    Address Mask Instruction Register Program Counter

For any of the instructions that are a part of the instruction set of the SRC, there are certain ____________ required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
Registers        Control signals                     Memory                       None of the given


The external interface of FALCON-A consists of a ________ data bus.
8-bit                 16-bit              24-bit   32-bit

Which one of the following registers holds the address of the next instruction to be executed?
Accumulator    Address Mask Instruction Register     Program Counter

In which one of the following techniques, the time a processor spends waiting for instructions to be fetched from memory is minimized?:
Perfecting      Pipelining         Superscalar operation            Speedup

__________ enable the input to the PC for receiving a value that is currently on the internal processor bus.
Select correct option:
LPC     INC4    LC       Cout

The processor must have a way of saving information about its state or context so that it can be restored upon return from the ------
Exception      Function                      Thread Stack


-----------is the ability of application software to operate on models of equipment newer than the model for which it was originally developed.
Backward compatibility                       Data migration                       Reverse engineering   Upward compatibility

_________ control signal allows the contents of the Program Counter register to be written onto the internal processor bus.
Select correct option:
INC4    LPC     PCout LC

Which one of the following registers stores a previously calculated value or a value loaded from the main memory?
Accumulator              Address Mask Instruction Register     Program Counter

Computer system performance is usually measured by the ---------------
Time to execute a program or program mix
The speed with which it executes programs
Processor’s utilization in solving the problems
Instructions that can be carried out simultaneously      I use  here  double dip  :d

The external interface of FALCON-A consists of a ____________ address bus.
8-bit     16-bit  24-bit   32-bit

Which one of the following register(s) that is/are programmer invisible and is/are required to hold an operand or result value while the bus is busy transmitting some other value?
Instruction Register     Memory address register        Memory Buffer Register      Registers A and C

-------------- performs the data operations as commanded by the program instructions.
Control                        Datapath         Structural RTL          Timing

_________ control signal allows the contents of the Program Counter register to be written onto the internal processor bus.
INC4    LPC     PCout             LC

The external interface of FALCON-A consists of a __________address bus and a _________ data bus.

8-bit , 8-bit       16-bit , 16-bit  16-bit , 24-bit   16-bit , 32-bit

-----------is the ability of application software to operate on models of equipment newer than the model for which it was originally developed.
Backward compatibility
Data migration
Reverse engineering
Upward compatibility

Which one of the following registers stores a previously calculated value or a value loaded from the main memory?
Accumulator
Address Mask
Instruction Register
Program Counter

Which one of the following register(s) contain(s) the address of the place the CPU wants to work with in the main memory and is/are directly connected to the RAM chips on the motherboard?
Instruction Register
Memory address register
Memory Buffer Register
Registers A and C

FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC is __________ wide.
Select correct option:
8-bits
16-bits
32-bits
64-bits

Question # 8 of 10 ( Start time: 08:27:54 PM ) Total Marks: 1
__________ enable the input to the PC for receiving a value that is currently on the internal processor bus.:
LPC
INC4
LC
Cout

The external interface of FALCON-A consists of a ________ data bus.
Select correct option:
8-bit
16-bit
24-bit
32-bit

For any of the instructions that are a part of the instruction set of the SRC, there are certain ____________ required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
Registers
Control signals
Memory
None of the given

CS 501 quiz no.1 solution. check this one

Attachments:

RSS

© 2021   Created by + M.Tariq Malik.   Powered by

Promote Us  |  Report an Issue  |  Privacy Policy  |  Terms of Service

.