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Advance Computer Architecture (CS501)

Assignment # 2

 

  Total marks = 20

                                                                                  Deadline Date = December 9, 2014

 

Please carefully read the following instructions before attempting assignment.

 

Rules for Marking

It should be clear that your assignment would not get any credit if:

 

  • The assignment is submitted after the due date.
  • The submitted assignment does not open or file is corrupt.
  • Strict action will be taken if submitted solution is copied from any other student or from the internet.

 

 

1)      You should concern recommended books to clarify your concepts as handouts are not sufficient.

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For any query, feel free to email at:

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Question No. 1                                                                                                                  10 Marks

 

Given are the assembly language instructions for Falcon-A processor. Write behavioral RTL description for each of the given instructions.

  1. Jpl r5, [20]
  2. Mul r3, r2, r1
  3. Div r5, r2, 6
  4. Load r4, [r3 +9]
  5. Shr r6, r3, 2

 

 

Question No. 2                                                                                                                  10 Marks

 

Write assembly language instructions for Falcon-E processor to implement the given arithmetic expression. 

C = ((5B + 4) ÷ 3) × 8A

 

any example of question 2???

instruction mul ra, rb, rc

This instruction is only present in this processor and not in SRC. The first three steps are exactly same as of other instructions and would fetch the mul instruction. In step T3 we will bring the contents of register R [rb] in the buffer register A at the input of ALSU. In step T4 we take the multiplication of A with the contents of R[rc] and put it at the output of the ALSU in two registers C and CH. CH would contain the higher 16-bits while register C would contain the lower 16-bits. Now these two registers cannot transfer the data in one bus cycle to the registers, since the width is 16-bits. So we need to have 2 timing steps, in T5 we transfer the higher byte to register R[0] and in T6 the lower 16-bits are transferred to the placeholder R[a]. As a result of multiplication instruction we need 3 timing steps for Instruction Fetch and 4 timing steps for Instruction Execution and 7 steps altogether.

div ra, rb, rc

jz ra, [c2] In first three steps of this table, the instruction is fetched. In T3 we set a 1- bit register "CON" to true if the condition is met

plz share any example of question #2

Dear Students Don’t wait for solution post your problems here and discuss ... after discussion a perfect solution will come in a result. So, Start it now, replies here give your comments according to your knowledge and understandings....

Check these handout examples and try to solve Question No.1

jpl (op-code= 16) In this instruction, the value contained in the register specified  page 94

in the field ra is checked, and if it is positive, the jump is taken.

 jpl r3, [label]   (R[3]≥0): PC ← PC+ (label-PC); 

 

mul r5, r7, r1                                                   page-97

 The RTL notation for this instruction will be

R[0] © R[5] ← R[7]*R[1]

4. div  (op-code= 5)                                        page-97

This instruction will divide the value of the register that is the second operand, by the

number in the register specified by the third operand, and assign the result to the

destination register.

  div r4, r7, r2 R[4]←R[0] ©R[7]/R[2],R[0]←R[0] ©R[7]%R[2]

 

load  (op-code= 29)

This instruction is to load a register from the memory. For instance, the

instruction

load r1, [r4 +15]

will add the constant 15 to the value stored in theregister r4, access the memory

location that corresponds to the number thus resulting, and assign the memory

contents of this location to the register r1; this is denoted in RTL by:

  R[1] ← M[R[4]+15]

Follow this example for Question No. 2

z = 4(a +b) – 16(c+58)             page 57 and 58 handouts

Solution A:

Notice that the

SRC does not have a multiply instruction.

multiplication with powers of 2 can be achieved by repeated shift left operations. 

ld R1, c ; c is a label used for a memory location
addi R3, R1, 58 ; R3 contains (c+58)
shl R7, R3, 4 ; R7 contains 16(c+58)
ld R4, a
ld R5, b
add R6, R4, R5 ; R6 contains (a+b)
shl R8, R6, 2 ; R8 contains 4(a+b)
sub R9, R7, R8 ; the result is in R9
st R9, z ; store the result in memory location z

Assuming Multiply instruction

ld R1, c                           ; c is a label used for a memory location
addi R3, R1, 58                ; R3 contains (c+58)
mul R7, R3, 4                  : R7 contains 16(c+58)
ld R4, a
ld R5, b
add R6, R4, R5                ; R6 contains (a+b)
mul R8, R6, 2                  ; R8 contains 4(a+b)
sub R9, R7, R8                 ; the result is in R9
st R9, z                           ; store the result in memory location z

no way ....... its wrong ....... 

here is a clue ....... 

is me jo b ho ga instruction k OP CODE k hisab se hoga ....... jo instruction us ka OP CODE ... like this ........

(op <4..0>=0) this will b used for addition ....... 

op code for mul , div instruction will be different .......... 

WISH U ALL THE best ...............

regards : GURU  <3

salro bro / sis i not able to identify your gender by name ....... 

u r giving the idea according to last assignment :) this will not b applicable here ...

coz now we are working on specific version of processor ....

so particular instruction set will be used according to that processor in this assign 

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