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Q1.                                                                                                                     10 marks

Consider  an  I/O  bus  that  can  transfer  5  bytes  of  data  in  one  bus  cycle and keeping in mind that the maximum frequency of the bus is 40 MHz. Suppose  that  a designer is considering to attach the following two components to this bus:

Hard drive, with a transfer rate of 80 Mbytes/sec and Video card, with a transfer rate of 140 Mbytes/sec. What will be the implications?

Q2.                                                                                                                     10 marks

Assume that the FALCONA is operating at a clock frequency of 1 GHz. Also, assume that the subi and the jnz instructions take 5 and 6 clock periods, respectively, to execute. Since these two instructions execute 65,535 times each, so you need to compute the execution time of this loop.

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### Replies to This Discussion

For complete assignment see the attached file please

Attachments:

Question 01:new components will operate at lower bandwidths.

Question 02

ET = (5+6) * 65535 / (1*109)
= 11 * 65535 / (1*109)
= 0.000720885

ET=(5+6)*65535/(1*10^9)

yeah thanks for the correction Anam

CS501_Assignment#3_Solution

Attachments:

thanks a lot       thankx

ye wala tekh ha

ET = (5+6) * 65535 / (1*109)
= 11 * 65535 / (1*109)
= 0.000720885

ya phir ye wala

ET= (5+6) x 65535/ (1x 107)
= 11 x 65535/ (1x 107)
= 720885/ (1 x 107)
= 0.072 sec   100% correct

Q1.                                                                                                                     10 marks

Consider  an  I/O  bus  that  can  transfer  5  bytes  of  data  in  one  bus  cycle and keeping in mind that the maximum frequency of the bus is 40 MHz. Suppose  that  a designer is considering to attach the following two components to this bus:

Hard drive, with a transfer rate of 80 Mbytes/sec and Video card, with a transfer rate of 140 Mbytes/sec. What will be the implications?

Solution:

The maximum frequency of the bus is 40 MHz.

Maximum bandwidth of this bus is 40 x 5 = 200 Mbytes/sec.

The demand for bandwidth from these two components will be 80 +140 =220 Mbytes/sec which is more than the 200 Mbytes/sec that the bus can provide.

Thus, if the designer uses these two components with this bus, one or both of these components will be operating at reduced bandwidth.

Q2.                                                                                                                     10 marks

Assume that the FALCONA is operating at a clock frequency of 1 GHz. Also, assume that the subi and the jnz instructions take 5 and 6 clock periods, respectively, to execute. Since these two instructions execute 65,535 times each, so you need to compute the execution time of this loop.

Solution:

Execution time of this loop can be calculated as:

ET = CPI x IC x T = CPI x IC / f

Where

CPI = clocks per instruction

IC = instruction count

T = time period of the clock,

And

f = frequency of the clock.

ET = (5+6) x 65535 / (1x109 )

ET = 0.0007209 sec

thanks a lot              thanx

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