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# CS501 - Advanced computer architecture_Spring_2015 Assignment # 1 Due date: Thursday, May 21, 2015

Assignment # 1

Marking scheme: 3 x 5 = 15

Due date: Thursday, May 21, 2015

Instructions:

It should be clear that your assignment will not get any credit if:

• The assignment is submitted after the due date.
• The submitted assignment does not open or file is corrupt.
• The assignment is found to be copied from the internet.
• The assignment is found to be copied from other student.
• The assignment submitted is not according to required file format (.doc).

Objective:

The objective of this assignment is:

• To assess your overall understanding of registers and operations.
• To assess your overall understanding of RTL notations operations.
• To assess your overall understanding of use arithmetic and logical operations in RTL.

Note:

• The assignment should be in .doc/docx format.
• Assignment 01 covers lecture 1-7. You can also consult reference books for help.
• Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

Question: Write (Register Transfer Language) RTL notations against the given five statements.

 S. No. Instruction Type Description RTL Notation 0 (Sample) The Falcon A arithmetic addition instruction of the type 4 (Sample) States that, the contents of Register R [2] are added with contents of Register R [5] and result is placed in R [4]. (Sample) R [4] ß  R [2] + R [5] 1 The Falcon-A arithmetic subtract instruction of the type 4, “Contents of Register R2 are subtracted by 56 and result is placed in R[1]” 2 The divde instruction of Falcon-A or type 4. The contents of R[6] are divided by R[3] and the result would be placed in two registers R[5] and R[0] because the result will always be of 32 bits, so two operent are of 16 bits are store in these two registers 3 A logical instruction of type 4 of Falcon-A processor performing “OR” operator The contents of R [3] and R [1] are places the result in R [4] after performing “OR” operator 4 The data transfer instruction of type C of Falcon-E processor Go to the IO address indicated by the contents of Register R [4] add 10 to it and after fetching the data from this IO port places it in the register R [7] 5 A data transfer instruction of the processor Falcaon-A and is a store instruction The contents of the Register R [3] are  placed in the memory location  given by the Register R[1] plus 13

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### Replies to This Discussion

good luck everybody

Our main purpose here discussion not just Solution

We are here with you hands in hands to facilitate your learning and do not appreciate the idea of copying or replicating solutions.

Dear Students Don’t wait for solution post your problems here and discuss ... after discussion a perfect solution will come in a result. So, Start it now, replies here give your comments according to your knowledge and understandings....

Falcon A type 4 on page no 96-97,

Falcone E type C on page no 128

Falcone A data transfer on page no 98

Dear Students Don’t wait for solution post your problems here and discuss ... after discussion a perfect solution will come in a result. So, Start it now, replies here give your comments according to your knowledge and understandings....

bohat easy assignment

this assignment from lec 9  and 10 :)

REGISTER TRANSFER LANGUAGE:
The symbolic notation used to describe the micro -operation transfer
among registers is known as register transfer language. A register
transfer language is a system for expressing in symbolic form the microoperation sequences among the registers of digital module.
EXAMPLE OF REGISTER TRANSFER LANGUAGE:
Suppose let us take an example of information transfer from one register
to another by means of replacement operator
R2<-R1
Which denotes transfer of content of register R1 into register R2.

0. (Sample) R [4]  R [2] + R [5]
1. R [1]  R [2] +(- 56)
2. R [5]  R [0] © R [6] / R [3]
3. R [4]  R [3] ~ R [1]
4. IO[R [4]+10] R[7]]

AND WORK ON IT AND THINK ABOUT IT
IT IS INTERESTING ASSIGNMENT

1. Sub r4, r2, 56

R[4] ←R[2]-56

2. div r5, r6, r3

3. or r4, r3, r1

R[4]← R[3]~R[1]

4. lds R7, R4(10)

R[7]←M[R[4]+10]

5. store r3, [r1+13]

M[R[1]+13]←R[3]

the 5th ans

R[3]←M[R[1]+13]

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