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CS501 All current final term paper Fall 2015 at one place from 5th March to 16th March 2015.

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Replies to This Discussion

plz cs 501 ka paper share kren mara kal paper hai

Today Paper 5 march 2015 .....

Attachments:

thanks for sharing

Good Work ... (y)

today my paper of cs501 5-3-2015

mcqs mostly new like

pipe line instruction increase what?option are latency,througput etc

 interrupts are applied to the......pin of the processor

other i forgot

1st q 2marks is

the branch address of the interrupt service routine is fixed btana tha yeh kon sa interrupt hai

overflow condition

similar and difference of raid 5,4

shift operation -24x2

ek btana tha k agar interrupt ko apply kia jaye cpu pe tu effect

name of three control signal and define 2

124 kb ko 32 byte mein cache line mein bit number btana tha

How many platters are required for a 40GB disk if there are 1024 bytes/sector, 2048 sectors per track
and 4096 tracks per platte yeh question tha bt value are different

prayer 4 me

if anyone have solution of these questions please Share.

Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines.   (Marks 5)
a) How many sets are there in the cache? 
b) How many bits of address are required to select a set in cache?

How many platters are required for a 40GB disk if there are 1024 bytes/sector, 2048 sectors per track 
and 4096 tracks per platte yeh question tha bt value are different

124 kb ko 32 byte mein cache line mein bit number btana tha

First Session 5 March 2015:

Mostly MCQs from moaaz updated file. Available in attachment.

  • Which operator is used to name registers, or part of registers, in the Register Transfer Language?
    •  := Ans
    • &
    • %
    • ©
  • Which is the last instruction of the ISR that is to be executed when the ISR terminates?
    • IRET
    • IRQ
    • INT
    • NMI
  • ----------the device usually means reading its status register every so often until the device's status changes to indicate that it has completed the request.
    • Executing
    • Interrupting
    • Masking
    • Polling
  • Identify the type of serial communication error condition in which A 0 is received instead of a stop bit (which is always a 1)?
    • Framing error 
    • Parity error
    • Overrun error
    • Under-run error
  • The______is m-bits wide and contains memory address generated by the CPU directly connected to the m-bit wide address bus Booth Recording
    • memory address register (MAR) 
    • memory Buffer Register(MBR)
    • Program counter (PC)
    • Instruction Register(IR)
  • A _______signal decides whether the input word should be shifted or bypassed.
    • Control Read
    • Shift/bypass 
    • Control Write
    • None of the given
  • Which one of the following registers store a previously calculated value or a value loaded from the main memory?
    • Accumulator
    • Address Mask
    • Instruction Register
    • Program Counter
  • By which file extension does the FALCON-A Assembler loads a FALCON-A assembly file?
    • .asmfa 
    • .org
    • .exe
    • .src
  • ___________ is the time for first bit of the message to arrive at the receiver including delays.
    • Transmission Time
    • Latency
    • Transport Latency
    • Time of Flight
  • Falcon-A Simulator loads a FALCON-A binary file with a ________ extension and presents its contents into different areas of the simulator.
    • .bin
    • .binfa 
    • .fa
    • None of the given

Short questions: 

  • If a DRAM has 512 rows and its refresh time is 9ms, what should be the frequency of row refresh operation on the average?

  • Find the average access time of a level of memory hierarchy if the hit rate is 80%. The memory access takes 12ns on a hit and 100ns on a miss.

  • Define Master and Slave components.
  • Explain NUXI problem.
  • Describe one advantage and disadvantage of Serial communication.
  • A network is using bus topology. If we replace it with Switch then what configuration will be changed? 
  • Add these two floating point numbers and mention all steps. 0.5(base 10), -0.4736(base10) 

Long Questions:

All questions from DMA and Cache topic. Don't miss Lecture 41 numerical problems.

Good Luck

Attachments:

today my paper of cs501
1 PROM stands for(2)marks
2 differenciate between CPU and Cache Memory .
3 Advantages of interrupts in a computer system.
4 how many minimum devices do you need to from RAID 0?
5 Wrap around effect
6 What is the Use of translation look aside buffer (TLB) and how it is implemented
inside the CPU .
7 using Shift operation , multiply given numbers -24X2
keeping the cache memory management into view ,explain
Write through Write back
in content of memory modules , describe the functionality of PROM
write the different mechanisms that can be used to avoid the device identification
design issue with respect to interrupt handling?

7

My paper CS501 3rd Group 2.00 PM

Attachments:

Good job adnan haider ... Much appreciated.

Great dear!

cs501 my todays 06-03-15 11am ppr
almost 50 % past
what is the use of .org directive in falsim?2mrks
expalin overflow condition? 2
what is term bus in computer systems?2
What is loss system? Explain 3mrks
Explain static property of hard disk?3mrks
what is DRam and it cell fuctionality?3mrks
shift operation to mutliply -24x2?5
write names of 3 control signals and explain any 2? 5
find the band width data was given.?5
baki yad ni arhy ab
do share ur all subjects pprs must all frnds..

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