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MCQS FROM MOAAZ AND 3 NEW THY
Q. SRC five-stage pipeline. arranged them,These stages were given.:(( 3 )
1. Instruction Fetch
2. Instruction decodes/operand fetches
3. ALU operation
4. Memory access
5. Register write
Q. Structured RTL for add ra, rb, rc operation? (3)
Q. Difference b/w branch and structural hazards.(5 marks)
Q.6 Write boolean equation of the logic circuit ?(5 marks)
Answer: -
PCout=T0+T3.(OP20+OP22)+T4.(OP16+OP17+OP18+OP19)
Thanks M Aftab and Waseem Gil...
Two operations of branch instruction [marks 2]
Discuss Falcon-A and SRC uni-bus implementation with respect to their bus width.
Reset operation
difference between memory address register and memory buffer register [3]
how many types of exceptions discuss any two [5]
jz ra,[c3] write RTL notation [5]
Qasim Ali thanks
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