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data hazard pipeline
Please share the whole paper and specially for mcqs.
MCQS FROM MOAAZ AND 3 NEW THY
Q. SRC five-stage pipeline. arranged them,These stages were given.:(( 3 )
1. Instruction Fetch
2. Instruction decodes/operand fetches
3. ALU operation
4. Memory access
5. Register write
Q. Structured RTL for add ra, rb, rc operation? (3)
Q. Difference b/w branch and structural hazards.(5 marks)
Q.6 Write boolean equation of the logic circuit ?(5 marks)
Thanks M Aftab and Waseem Gil...
Two operations of branch instruction [marks 2]
Discuss Falcon-A and SRC uni-bus implementation with respect to their bus width.
difference between memory address register and memory buffer register 
how many types of exceptions discuss any two 
jz ra,[c3] write RTL notation 
Qasim Ali thanks
kindly mujy ye bta dy koe k is ques me 8GB kesy aa gya?
1024 bytes/sector X 2048 sector per track X 4096 track per platter