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CS501 ALL Current Mid Term Papers Spring 2015 & Past Mid Term Papers at One Place from 20 June 2015 ~ 01 July 2015

CS501 ALL Current Mid Term Papers Spring 2015 & Past Mid Term Papers at One Place from 20 June 2015 ~ 01 July 2015

 

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Share Your Current mid Term Papers (Questions/Pattern) 20 June 2015 ~ 01 July 2015 to help each other. Thanks

 

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data hazard pipeline

Please share the whole paper and specially for mcqs.

MCQS FROM MOAAZ AND 3 NEW THY

Q. SRC five-stage pipeline. arranged them,These stages were given.:(( 3 )

1. Instruction Fetch
2. Instruction decodes/operand fetches
3. ALU operation

4. Memory access
5. Register write

 

Q. Structured RTL for add ra, rb, rc operation? (3)

Q. Difference b/w branch and structural hazards.(5 marks)

Q.6 Write boolean equation of the logic circuit ?(5 marks)

 Answer: - 
PCout=T0+T3.(OP20+OP22)+T4.(OP16+OP17+OP18+OP19)

Thanks M Aftab and Waseem Gil...

Two operations of branch instruction [marks 2]

Discuss Falcon-A and SRC uni-bus implementation with respect to their bus width. 

Reset operation 

difference between memory address register and memory buffer register [3]

how many types of exceptions discuss any two [5]

jz ra,[c3] write RTL notation [5]

Qasim Ali thanks 

Always mention 

kindly mujy ye bta dy koe k is ques me 8GB kesy aa gya?

1024 bytes/sector X 2048 sector per track X 4096 track per platter

= 8GB

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