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 + Qurat
Ap ne paper kis time pe diya tha?

cs501 Current Midterm Paper
40% paper from past papers:
5,6 mcqz from FALCON 's topic.
1.Write features of FALOCON-E. (3)
2.Describe the "Trace and debugging" exception.
(3)
3.FALCON -E k according likhna tha
i.Number of register
ii)size of register
iii)Memory space between word (5)
4.Pipelining ke implementation (5

1.Write features of FALOCON-E. (3)
The following features characterize the FALCON-E
• Fixed instruction size, which is 32 bits. So the instruction size is 1 word.
• All ALU instructions have three operands
• Memory access is possible only through the load and store instructions. Also, only
a limited addressing modes are supported by the FALCON-E

4.Pipelining ke implementation (5
ANS:
three parts:
1. Adapting the instructions to pipelined execution
2. Designing the pipelined data path
3. Generating control signals

Q3: briefly explain instruction decode/operand fetch stage of pipeline.
Ans:
In this stage the instruction are fetched from the register file.
If the instruction is add r1, r2, r3 the
registers r2 and r3 will be read into the temporary pipeline
registers.
Q3 : How many types of Exception occurs in a machine? ecplain it.

ANS:
external and internal exceptions

External exceptions generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock
Q6 Write 2 difference Eagle and modified eagle.
Ans:
The EAGLE
is an accumulator-based machine. It is a simple processor that will help us in our understanding of the processor design process.
The Modified EAGLE
The modified EAGLE is an improved version of the processor EAGLE.
It is a processor that will help us in our understanding simple, yet complex enough to illustrate the various concepts of a processor design.

Q1: any 3 instructions which belong to type B instruction format of falcon-E processor.
Ans:
push (op-code = 8)
pop (op-code = 9)
ld (op-code = 10)
st (op-code = 12)

1. What do you understand about machine exception.
Ans:• Anything that interrupts the normal flow of execution of instructions in the processor is called an exception.
• Exceptions may be generated by an external or internal event such as a mouse click or an attempt to divide by zero etc.
• External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock)
Q1 : Write any 3 Step involved in designing and implemntation of Pipeline machine.
1. Instruction fetch
the instruction is fetched from the
instruction memory in this stage.
.
2. Instruction decode/operand fetch
In this stage the instruction are fetched from the register file.
If the instruction is add r1, r2, r3 the
registers r2 and r3 will be read pipeline
registers.
3. ALU5 operation
the instruction is fetched from the ALU
such as addition,subtraction, etc.

The result is stored into temporary pipeline
registers. In case of a memory access such as a load or a store
instruction, the ALU calculates the effective memory address
in this stage.

Anyone give me the Answer of these Questions?????

Q1 :Write the Following Statement of an arithematic instruction using RTL if opcode is 0 instruction is add the value in register rb and rc are added and result stoed in regsra.
Q2: functionality of RTL?
Q3: Write a structural RTL for Shift instruction for Uni-Bus data path implementation.
shiftr ra, rb, c1?
Q4.Which control signal are used for write value of MBR( Memory Buffer Register) into IR( Instruction Register). 5.D:R3←R5
MAR←IR (something like that I don't remember exactly
Q5: The reset operation of a processor are? explain briefly?

Q6 : Write down any four characteristics of SPAC register windows.
Q7.Describe the "Trace and debugging" exception.

Q8.FALCON -E k according likhna tha
i.Number of register
ii)size of register
iii)Memory space between word (5)

My Today cs501 Paper @ 10:30 Muhammad Shahroz Munir :)
Q.1 Structural RTL for addition
instruction
add ra, rb, rc
Q.2 Structural RTL for add immediate instruction
addi ra, rb, c1
Q3 Write down any four characteristics of SPAC register windows.
5 marks
Q4 difference between external and internal exceptions?
Q5 uni- bus path implementation difference between PC and IR
Q6 Which register holds the address of the next instruction to be executed in the processor?

Q1 : Write any 3 Steps involved in designing and implementation of Pipeline machine.

Designing a pipelined implementation

In this section we will discuss the various steps involved in designing a pipeline. Broadly speaking they may be categorized into three parts:

1. Adapting the instructions to pipelined execution

The instruction set of a non-pipelined processor is generally different from that of a pipelined processor. The instructions in a pipelined processor should have clear and definite phases, e.g., add r1, r2, r3. To execute this instruction, the processor must first fetch it from memory, after which it would need to read the registers, after which the actual addition takes place followed by writing the results back to the destination register. Usually register-register architecture is adopted in the case of pipelined processors so that there are no complex instructions involving operands from both memory and registers. An instruction like add r1, r2, a would need to execute the memory access stage before the operands may be fed to the ALU. Such flexibility is not available in a pipelined architecture.

2. Designing the pipelined data path

Once a particular instruction set has been chosen, an appropriate data path needs to be designed for the processor. The data path is a specification of the steps that need to be followed to execute an instruction. Consider our two examples above For the instruction add r1, r2, r3: Instruction Fetch – Register Read – Execute – Register Write, whereas for the instruction add r1, r2, a (remember a represents a memory address), we have Instruction Fetch – Register Read – Memory Access – Execute – Register Write The data path is defined in terms of registers placed in between these stages. It specifies how the data will flow through these registers during the execution of an instruction. The data path becomes more complex if forwarding or bypassing mechanism is added to the processor.

3. Generating control signals

Control signals are required to regulate and direct the flow of data and instruction bits through the data path. Digital logic is required to generate these control signals.

Q2 : Write down any four characteristics of SPARC register windows.

As with the Berkeley RISC, the SPARC makes use of register windows. Each window gives addressability to 24 registers, and the total number of windows is implementation dependent and ranges from 2 to 32 windows. It supports 8 windows, using a total of 136 physical registers this seems a reasonable number of windows. Physical registers 0 through 7 are global registers shared by all procedures. Each procedure sees logical registers 0 through 31. Logical registers 24 through 31, referred to as ins, are shared with the calling (parent) procedure; and logical registers

8 through 15, referred to as outs, are shared with any called (child) procedure. These two portions overlap with other windows. Logical registers 16 through 23, referred to as locals, are not shared and do not overlap with other windows. With the SPARC register architecture, it is usually not necessary to save and restore registers for a procedure call. The compiler is simplified because the compiler need be concerned only with allocating the local registers for a procedure in an efficient manner and need not be concerned with register allocation between procedures.

 

 

 

Q3: How many types of Exception occur in a machine? Explain it.

Types of Exception

Program Exceptions

These are exceptions raised during the process of decoding and executing the instruction. Examples are illegal instruction, raised in response to executing an instruction which does not belong to the instruction set. Another example would be the privileged instruction exception.

Hardware Exceptions

There are various kinds of hardware exceptions. An example would be of a timer which raises an exception when it has counted down to zero.

Trace and debugging Exceptions

Variable trace and debugging is a tricky task. An easy approach to make it possible is through the use of traps. The exception handler which would be called after each instruction execution allows examination of the program variables.

Nonmaskable Exceptions

These are high priority exceptions reserved for events with catastrophic consequences such as power loss. These exceptions cannot be suppressed by the processor under any condition. In case of a power loss the processor might try to save the system state to the hard drive, or alert an alternate power supply.

Interrupts (External Exceptions)

Exception handlers may be written for external interrupts, thus allowing programs to respond to external events such as keyboard or mouse events.

Q4 :Write the Following Statement of an arithmetic instruction using RTL if opcode is 0 instruction is add the value in register rb and rc are added and result stoed in regs ra.

add (op-code = 0 )

This instruction adds contents of a register to those of another register, and assigns to the destination register. An example:

and r4, r3, r5

R[4] ← R[3] +R[5]

Q5 : What is the function of the "REset" Operation of Processor.

The reset operation

Reset operation is required to change the processor’s state to a known, defined value. The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value. The control step counter is set to zero so that operation is restarted from the instruction fetch phase of the next instruction. The PC is reloaded with a predefined value usually to execute a specific recovery or initializing program.

In most implementations the reset instruction also clears the interrupt enable flags so as to disable interrupts during the initialization operation. If a condition code register is present, the reset instruction usually clears it, so as to clear any effects of previously executed instructions. The external flags and processor state registers are usually cleared too.

Reset operation in SRC

Hard Reset

The SRC should perform a hard reset upon receiving a start (Strt) signal. This initializes the PC and the general registers.

Soft Reset

The SRC should perform a soft reset upon receiving a reset (rst) signal. The soft reset results in initialization of PC only.

The reset signal in SRC is assumed to be external and asynchronous.

Q6 Write 2 difference Eagle and modified eagle.

The modified EAGLE is also an accumulator-based processor. It is a simple, yet complex enough to illustrate the various concepts of a processor design.

The modified EAGLE is characterized by

• A special purpose register, the 16-bit accumulator: ACC

• 8 General Purpose Registers of the CPU: R0, R1, …, R7; 16-bits each

• Two 16-bit system registers transparent to the programmer are the Program

Counter (PC) and the Instruction Register (IR).

• Memory word size: 16 bits

• Memory space size: 216 bytes

• Memory organization: 216 x 8 bits

• Memory is accessed in 16 bit words (i.e., 2 byte chunks)

• Little-endian byte storage is employed

1. What do you understand about machine exception?

Anything that interrupts the normal flow of execution of instructions in the processor is called an exception.

• Exceptions may be generated by an external or internal event such as a mouse click or an attempt to divide by zero etc.

• External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock)

The exception process allows instruction flow to be modified, in response to internal or external events or anomalies. The normal sequence of execution is interrupted when an exception is thrown.

 

2 Which control signal are used for write value of MBR( Memory Buffer Register) into IR( Instruction Register).

The instruction register IR is loaded with data from the MBR, so we need two control signals, ’MBRout’ to enable its tri-state buffers and the other signal required is the load signal for IR register ‘LIR’.

 

3. Write RTL for the call instruction.

Structural RTL for the call instruction

call ra, rb

In this instruction we need to give the control to the procedure, sub-routine or to another address specified in the program. First three steps would fetch the call instruction. In step T3 we store the present contents of PC in to the buffer register C and then from C we transfer the data to the register ra in step T4. As a result register ra would contain the original contents of PC and this would be a pointer to come back after executing the sub-routine

and it would be later used by a return instruction. In step T5 we take the contents of register rb, which would actually indicate to the point where we want to go. So in step T6 the contents of C are placed in PC and as a result PC would indicate the position in the memory from where new execution has to begin.

4 Write the  structural RTL to add ra ,rb rc.

Structural RTL for addition instruction

add ra, rb, rc

The table of add instruction is almost same as of sub instruction except in timing step T4 we have + sign for addition instead of – sign as in sub instruction. Other instructions that belong to the same group are ‘and’, ‘or’ and ‘sub’.

5.D:R3←R5

  MAR←IR (something like that I don't remember exactly


Q1: any 3 instructions which belong to type B instruction format of falcon-E processor.

Five instructions belong to the type B format of instructions. These are:

push (op-code = 8) /This instruction is used to push the contents of a register onto the stack. For instance, the instruction,

push R4 /will push the contents of register R4 on top of the stack

• pop (op-code = 9)/ The pop instruction is used to pop a value from the top of the stack, and the value is read into a register. For example, the instruction

pop R7/ will pop the upper-most element of the stack and store the value in register R7

• ld (op-code = 10) / This instruction with op-code (10) loads a memory word from the address

specified by the immediate filed value. This word is brought into the operand

register ra. For example, the instruction, ld R7, 1254h/ will load the contents of the memory at the address 1254h into the register R7.

• st (op-code = 12) / The store instruction of (opcode 12) stores a value contained in the register

operand into the memory location specified by the immediate operand field. For example, in

st R7, 1254h / the contents of register R7 are saved to the memory location 1254h.

 

Q2: functionality of RTL?

RTL stands for Register Transfer Language. The Register Transfer Language provides a formal way for the description of the behavior and structure of a computer. The RTL facilitates the design process of the computer as it provides a precise, mathematical representation of its functionality.

Q3: briefly explain instruction decodes/operand fetches stage of pipeline.

Instruction decode/operand fetch: In this stage the operands for the instruction are fetched from the register file. If the instruction is add r1, r2, r3 the registers r2 and r3 will be read into the temporary pipeline registers.

Q4: Write a structural RTL for Shift instruction for Uni-Bus data path implementation.
shiftr ra, rb, c1?

Shift instructions are rather complicated in the sense that they require extra hardware to hold and

decrement the count. For an ALSU that can perform only single bit shifts, the data must be repeatedly cycled through the ALSU and the count decremented until it reaches zero. This approach presents some timing problems, which can be overcome by employing multiple-bit shifts using a barrel shifter.

The structural RTL for shr ra, rb, rc or shr ra, rb, c3 is given in the corresponding table shown. Here n represents a 5-bit register; IR bits 0 to 4 are copied in to it. N is the decimal value of the number in this register. The actual shifting is being done in step T5. Other instructions that will have similar tables are: shl, shc, shra

e.g., for shra, T5 will have C← (NαR [rb] <31>) © R[rb] <31...N>;

Q5: How many types of instructions are available in SRC? Name them. What is the format of each of these instructions?

The SRC uses a five-stage pipeline. Those five stages are given below:

1. Instruction Fetch

2. Instruction decode/operand fetch

3. ALU operation

4. Memory access

5. Register write

 

Q6: The reset operation of a processor is? explain briefly? 

Reset operation is required to change the processor’s state to a known, defined value. The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value. The control step counter is set to zero so that operation is restarted from the instruction fetch phase of the next instruction. The PC is reloaded with a predefined value usually to execute a specific recovery or initializing program.

In most implementations the reset instruction also clears the interrupt enable flags so as to disable interrupts during the initialization operation. If a condition code register is present, the reset instruction usually clears it, so as to clear any effects of previously executed instructions. The external flags and processor state registers are usually cleared too.

The reset instruction is mainly used for debugging purposes, as most processors halt operations immediately or within a few cycles of receiving the reset instruction. The processors state may then be examined in its halted state.

Some processors have two types of reset operations. Soft reset implies initializing PC and interrupt flags. Hard reset initializes other processor state registers in addition to PC and interrupts enable flags. The software reset instruction asserts the external reset pin of the processor.

 


1.Write features of FALOCON-E. (3)

 

FALCON-E Features

The following features characterize the FALCON-E

  • • Fixed instruction size, which is 32 bits. So the instruction size is 1 word.
  • • All ALU instructions have three operands
  • • Memory access is possible only through the load and store instructions. Also, only a limited addressing modes are supported by the FALCON-E


2.Describe the "Trace and debugging" exception.(3)

Trace and debugging Exceptions

Variable trace and debugging is a tricky task. An easy approach to make it

possible is through the use of traps. The exception handler which would be called

after each instruction execution allows examination of the program variables.

3.FALCON -E k according likhna tha
i.Number of register (8 general purpose registers named R0….R7)
ii)size of register (each register is 4 bytes longwhic makes together 32-bit resisters)
iii)Memory space between word  is 2^32 bytes

Q6 Write 2 difference Eagle and modified eagle.
Ans:
The EAGLE is an accumulator-based machine. It is a simple processor that will help us in our understanding of the processor design process.
The Modified EAGLE  is an improved version of the processor EAGLE. 
It is a processor that will help us in our understanding simple, yet complex enough to illustrate the various concepts of a processor design.

Q1: any 3 instructions which belong to type B instruction format of falcon-E processor.
Ans: 
push (op-code = 8)
pop (op-code = 9)
ld (op-code = 10)
st (op-code = 12)

Q1 : Write any 3 Step involved in designing and implemntation of Pipeline machine.
1. Instruction fetch : the instruction is fetched from the instruction memory in this stage.
.
2. Instruction decode/operand fetch:  In this stage the instruction are fetched from the register file. If the instruction is add r1, r2, r3 the registers r2 and r3 will be read pipeline registers.
3. ALU5 operation: the instruction is fetched from the ALU such as addition,subtraction, etc.

The result is stored into temporary pipeline registers. In case of a memory access such as a load or a store instruction, the ALU calculates the effective memory address in this stage.

 

EAGLE: Instruction Formats

There are five instruction formats for the EAGLE. These are

Type Z Instruction Format

The Z format instructions are half-word (1 byte) instructions, containing just the op-code field of 8 bits, as shown

Type Y Instruction Format

The type Y instructions are also half-word. There is an op-code field of 5 bits, and a register operand field ra.

Type X Instruction Format

Type X instructions are also half-word instructions, with a 2-bit op-code field, and two 3-bit operand register fields, as shown.

Type W instruction format

The instructions in this type are 1- word (16-bit) in length. 8 bits are reserved for the op-code, while the remaining 8 bits form the constant (immediate value) field.

Type V instruction format

Type V instructions are also 1-word instructions, containing an op-code field of 5 bits, an operand register field of 3 bits, and 8 bits for a specifying a constant.

 

Which control signal of the control unit should ber activated for the following function:

1. Writing data from bus to register  2. Writing data from register to bus

First of all, if the condition opc = 1 is met, the contents of the first operand register, R3, are transferred to the temporary register A through the bus. This is done by activating R3out. It lets the contents of the register R3 to be loaded on the bus. At the same time, applying a logical high input to LA enables the load for the register A. This lets the binary number on the bus (the contents of register R3) to be loaded into the register A. The next step is to enable R2out to load the contents of the register R2 onto the bus. As can be observed from the figure, the output of the register A is one of the inputs to the 4- bit adder; the other input to the adder is the bus itself. Therefore, as the contents of register R2 are loaded onto the bus, both the operands are available to the adder. The output can then be stored to the register RC by enabling its write. So a high input is applied to LC to store the result in register RC. The third and final step is to store (transfer) the resultant number in the destination register R4. This is done by enabling Cout, which writes the number onto the bus, and then enabling the read of the register R4 by activating the control signal to LR4. These steps are summarized in the given table.

LMBR: This enables the “write” for the register MBR. When this signal is activated,

whatever value is on the bus, can be written into the MBR.

Thanks

this may be to much for MID term by Abuzar Ghaffari mc130201311

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