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Advance Computer Architecture(CS501)

Assignment # 02
Spring 2021

 

Total marks = 20                                                                              

 

Deadline Date
June 4, 2021

 

 

Please carefully read the following instructions before attempting the assignment.

 

RULES FOR MARKING

It should be clear that your assignment would not get any credit if:

·        The assignment is submitted after the due date.

·        The submitted assignment does not open or the file is corrupt.

·        Strict action will be taken if the submitted solution is copied from any other student or the internet.

 

You should consult the recommended books to clarify your concepts as handouts are not sufficient.

 

You are supposed to submit your assignment in Doc or Docx format.

Any other formats like Scan Images, Pdf, Zip, Rar, Ppt and Bmp, etc will not be accepted.

 

OBJECTIVE

The objective of this assignment is to increase the learning capabilities of the students about

 

·        Register Transfer Language

·        External Falcon-A CPU Interface

·        Falcon-A Address Bus and Data Bus

 

 

 

NOTE

No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignments in the last hour of the deadline. It is recommended to upload the solution file at least two days before its closing date.

 

If you find any mistake or confusion in the assignment (Question statement), please consult with your instructor before the deadline. After the deadline, no queries will be entertained in this regard.

 

 

For any query, feel free to email at:

cs501@vu.edu.pk

 

 

 

 

 

 

Question No. 01                                                                                                         10 Marks

Write a FALCON-A instruction for each of the below given RTLDescription.

 

RTL Description

Instruction

R[1]←R[0] ©R[3]/R[2],R[0]←R[0] ©R[3]%R[2]

 

R[1] ← R[2] ~ R[3]

 

R[1] ←R[2] + (11α 3<4>)© 3<4..0>

 

 

R[1]← M[R[2]+ (11α 6<4>)© 6<4..0>]

 

 

R[3] ← (8α12<7>)©12<7..0>

 

 

 

 

Question No. 02                                                                                                            10 Marks

Consider the below-given tables. Table 1 shows the contents stored at different memory addresses. Table 2 shows the contents stored in different registers.

 

Memory Address

Memory Contents

 

Register

Register Contents

ABD0h

40h

 

R[0]

0021h

ABD1h

89h

 

R[1]

1212h

ABD2h

67h

 

R[2]

ABBCh

ABD3h

21h

 

R[3]

A00Ah

ABD4h

33h

 

R[4]

0AB1h

ABD5h

52h

 

R[5]

6023h

ABD6h

60h

 

R[6]

FF00h

ABD7h

00h

 

R[7]

ABCDh

Table 1: Memory Contents

 

Table2: Register Contents

 

 

What will the contents of the address bus and data bus after each of the instructions be executed?

 

  • LOAD R1, [R2+20]
  • STORE R0, [R7+7]

 

 

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