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# CS501 - Assignment no - 2

 Assignment No. 02 (Graded Assignment) Semester: Fall 2013 CS501: Advanced Computer Architecture Total Marks: 20 Due Date 5 December, 2013

Instructions

Please read the following instructions carefully before assignment submission.

It should be clear that your assignment will not get any credit if:

• The assignment is submitted after the due date.
• The submitted assignment does not open or file is corrupt.
• The assignment is found to be copied from the internet.
• The assignment is found to be copied from other student.
• The assignment submitted is not according to required file format (.doc).

Objective

The objective of this assignment is:

• To assess your overall understanding of Computer Architecture and Organization.
• To assess your overall understanding of RTL (Register Transfer Language) instructions.
• To assess your overall understanding of Fetch, Decode and Execute Cycle clock in CPU.

Note:

• The assignment should be in .doc format.
• Assignment .02 covers lecture 8-14. You can also consult reference books for help.
• Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

Question 1:                                                                                     Marks 15

Suppose you have eight general purpose registers ( ra, rb, rc, rd, re, rf, rg and rh). You are required to complete the instruction fetch-execute cycle of register-to-register sub (subtract) and add (addition) instructions. Also specify the corresponding type of structural RTL.

You are required to solve:

1.1.   Type of structural RTL (Register Transfer Language)                               1 Mark

1.2.   Fetch-execute cycle of the register-to-register Add instruction                    7 Marks

1.3.   Fetch-execute cycle of the register-to-register Sub instruction             7 Marks

Question  2:                                                                 Marks 1+1+1+1+1=5

.

Briefly explain the following RTL (Register Transfer Language) notations                                              i.            R [4] ß  R [3] + (-32)

ii.            R[2] ←R[0] ©R[5]/R[7]

iii.            R [1] ß  R [2] ~ R [5]

iv.            IO[R [2]+1]ß  R[1]]

v.            M[R [2] +14]    ß   R [4]

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### Replies to This Discussion

Lets discuss the solution..............

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RTL is used in the logic design phase of the integrated circuit design cycle.

An RTL description is usually converted to a gate-level description of the circuit by a logic synthesis tool. The synthesis results are then used by placement and routing tools to create a physical layout.

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Aoa

kay ya pay kartay b han.yan time waiste he ha.

plz start disc

ques 2 solution is in lecture 8

ques 1 ki bilkul b smj nai aa rai mjy plz discuss q no 1

qno1 k first part me type of instruction of rtl me ye btana hy na k type kon c hy A,B,C,D????????????

kia yaaaarrrrr 1st assignment me 14 marks a gye bt wo non-graded the or jo graded hy us ka sir pair hi ni mil rha:(

first question first part, what type? opcode of add is = 1? or sub = 3?

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