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# CS501 - Assignment no - 2

 Assignment No. 02 (Graded Assignment) Semester: Fall 2013 CS501: Advanced Computer Architecture Total Marks: 20 Due Date 5 December, 2013

Instructions

It should be clear that your assignment will not get any credit if:

• The assignment is submitted after the due date.
• The submitted assignment does not open or file is corrupt.
• The assignment is found to be copied from the internet.
• The assignment is found to be copied from other student.
• The assignment submitted is not according to required file format (.doc).

Objective

The objective of this assignment is:

• To assess your overall understanding of Computer Architecture and Organization.
• To assess your overall understanding of RTL (Register Transfer Language) instructions.
• To assess your overall understanding of Fetch, Decode and Execute Cycle clock in CPU.

Note:

• The assignment should be in .doc format.
• Assignment .02 covers lecture 8-14. You can also consult reference books for help.
• Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

Question 1:                                                                                     Marks 15

Suppose you have eight general purpose registers ( ra, rb, rc, rd, re, rf, rg and rh). You are required to complete the instruction fetch-execute cycle of register-to-register sub (subtract) and add (addition) instructions. Also specify the corresponding type of structural RTL.

You are required to solve:

1.1.   Type of structural RTL (Register Transfer Language)                               1 Mark

1.2.   Fetch-execute cycle of the register-to-register Add instruction                    7 Marks

1.3.   Fetch-execute cycle of the register-to-register Sub instruction             7 Marks

Question  2:                                                                 Marks 1+1+1+1+1=5

.

Briefly explain the following RTL (Register Transfer Language) notations                                              i.            R [4] ß  R [3] + (-32)

iii.            R [1] ß  R [2] ~ R [5]

iv.            IO[R [2]+1]ß  R[1]]

v.            M[R [2] +14]    ß   R [4]

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### Replies to This Discussion

Instructor replayed only used general purpose register...

plz complte sol upload kr dan

Kindly explain these

i.  R [4] ß  R [3] + (-32)

iii. R [1] ß  R [2] ~ R [5]

iv. IO[R [2]+1]ß  R[1]]

v.M[R [2] +14]    ß   R [4]

In Question 1. Also specify the corresponding type of structural RTL.

koi bata skta ha is ki types kiya hain ??????????

type of ADD and SUB instructions are FALCON A.

Suppose we want to add as ra=rb+rc+rd+re+rf+rg+rh

This operation  can be done in the following manner

1. Ra=rb+rc
2. Rd=ra+re
3. Rf=rd+rg
4. Rh=rh+rf

Dear All.......Please upload and past the correct solution as we have no more time now

Type of structural RTL (Register Transfer Language)

1.2.   Fetch-execute cycle of the register-to-register Add instruction

1.3.   Fetch-execute cycle of the register-to-register Sub instruction

thanks Mahnoor Ali

aoa

ye to t5 tk hy jb k i think humin 8 register tk find kerna hy plz guide me in this regard plz

 Student's Message: Msg No. 613885
 Subject: concatenation could we use concatenation with add & sub instructions? Post Your Comments Other Students' Comments: 0 Instructor's Reply: Dear student   In assignment questions there is no need of concatenation. You have eight registers and you are required to use these 8 register for making the fetch execution cycle. Little bit of trick involved in this assignment question that by getting the sequence hint from the given example and solving the assignment accordingly with their corresponding timing steps.  You must concentrate on the given example and listen to the video lecture 12 to figure out how to solve the assignment question Regards

it is register to register transfer.  for this Falcon A   or   Falcon E ??

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