Plz Discuss this assignment
Assignment No. 05
CS501: Advanced Computer Architecture
Total Marks: 20
Due Date: 03-07-13
Please read the following instructions carefully before assignment submission.
It should be clear that your assignment will not get any credit if:
The objective of this assignment is:
Suppose we have a benchmark that executes in 100 seconds of elapsed time, where 90 seconds is CPU time and the rest is I/O (Input/output) time. If CPU time improves by 50% per year for the next five years but I/O time doesn’t improve, how much faster will our program run at the end of five years?
You are required to calculate the CPU improved performance and improved elapsed time.
Question No 2: (4 marks)
Consider a 20 MIPS (Microprocessor without Interlocked Pipeline Stages) processor with several input devices attached to it, each running at 1000 characters per second. Assume that it takes 17 instructions to handle an interrupt. If the hardware interrupt response takes 1msec, what is the maximum number of devices that can be handled simultaneously?
NOTE: Theoretical answer will not be considered
Question No 3: (6 Marks)
If we want the lowest latency for an I/O operation to a single I/O device; while in terms of lowest impact on processor utilization from a single I/O device then what will be the orders/arrangements of Interrupt driven, DMA(Direct Memory Access) and polling in both scenarios? Explain reasons.
NOTE: Give answer within 3-5 lines. Otherwise answer will not be considered.
GOOD LUCK J
i got it!!!!
Q1 is the geometric series like problem n to calculate it we form a series n find the common ratio..
It is CPU time = 90 as it improves by 50% = 50/100=5/10 per year
then 90+ [90+90(5/10)]+[90+90(5/10)^2]+........
= 90+[90(1+5/10)] + [90(1+(5/10)^2]+......
here common ratio =1.5
as performance improves so it wud decrease that is
90/1.5= 60 and so on so forth....
gud work and thanks for removing the confusion
good work thanks
1st question mai CPU improved performance and improved elapsed time k answer mai unit seconds ho ga na ?
Q#3 ka solution nhi aaya,
solution chahye , arrangements with reasons.....
OK . q # 3 is veryvery easy
3 to 5 lines main DMA, intrrupt i/o our polling ko compair kro .
our btao k DMA kaisy better hy interrupt i/o sy our interrupt i/o kaisy better hy polling sy .
Welcome back Zahoor bro
Arrangements that i found from net
lowest latency for an I/O operation to a single I/O device, the order is of polling, DMA, and interrupt driven.
lowest impact on processor utilization from a single I/O device, the order is DMA, interrupt driven, and polling.
Thx B sis