www.vustudents.ning.com

# CS501 ASSIGNMENT NO. 5, DISCUSSION AND SOLUTION( DUE DATE: 3RD JULY, 2013)

Plz Discuss this assignment

 Assignment No. 05 Semester: Spring 2013 CS501: Advanced Computer Architecture Total Marks: 20 Due Date:  03-07-13 Instructions Please read the following instructions carefully before assignment submission. It should be clear that your assignment will not get any credit if: The assignment is submitted after the due date. The submitted assignment does not open or file is corrupt. The assignment is found to be copied from the internet. The assignment is found to be copied from other student. The assignment submitted is not according to required file format (.doc). Objective The objective of this assignment is: To assess your overall understanding of Computer Architecture and Organization To assess your overall understanding of Computer processing To assess your overall understanding of DMA, Polling and interrupts Note: The assignment should be in .doc format. Assignment .05 covers lecture 25-31. You can also consult reference books for help. Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

Question No 1:
(10 marks)

Suppose we have a benchmark that executes in 100 seconds of elapsed time, where 90 seconds is CPU time and the rest is I/O (Input/output) time. If CPU time improves by 50% per year for the next five years but I/O time doesn’t improve, how much faster will our program run at the end of five years?

You are required to calculate the CPU improved performance and improved elapsed time.

 After n years CPU/ time I/O time Elapsed time % I/O time 0 (Current Year) 1 2 3 4 5

NOTE: Theoretical answer will not be considered

______________________________________________________________________

Question No 2:                                                                                                      (4 marks)

Consider a 20 MIPS (Microprocessor without Interlocked Pipeline Stages) processor with several input devices attached to it, each running at 1000 characters per second. Assume that it takes 17 instructions to handle an interrupt. If the hardware interrupt response takes 1msec, what is the maximum number of devices that can be handled simultaneously?

NOTE: Theoretical answer will not be considered

______________________________________________________________________

Question No 3:                                                                                                        (6 Marks)

Scenarios discussion:

If we want the lowest latency for an I/O operation to a single I/O device; while in terms of lowest impact on processor utilization from a single I/O device then what will be the orders/arrangements of Interrupt driven, DMA(Direct Memory Access) and polling in both scenarios? Explain reasons.

NOTE: Give answer within 3-5 lines. Otherwise answer will not be considered.

______________________________________________________________________

GOOD LUCK J

Views: 8051

Attachments:

### Replies to This Discussion

i got it!!!!

Q1 is the geometric series like problem n to calculate it we form a series n find the common ratio..

It is CPU time = 90 as it improves by 50% = 50/100=5/10 per year

then 90+ [90+90(5/10)]+[90+90(5/10)^2]+........

= 90+[90(1+5/10)] + [90(1+(5/10)^2]+......

= 90+90(1.5)+90[1.5]^2+.....

here common ratio =1.5

as performance improves so it wud decrease that is

90/1.5= 60 and so on so forth....

90/1.5

gud work and thanks for removing the confusion

good work thanks

thanks zeemal

thx zeemal

common ratio for the example given in table in CS501 handouts it is 1.4

1st question mai CPU improved performance and improved elapsed time    k answer mai unit seconds ho ga na ?

Q#3 ka solution nhi aaya,
solution chahye , arrangements with reasons.....

OK . q # 3 is veryvery easy

3 to 5 lines main DMA, intrrupt i/o our polling ko compair kro .

our btao k DMA kaisy better hy interrupt i/o sy our interrupt i/o  kaisy better hy polling sy .

Welcome back Zahoor bro

Arrangements that i found from net

lowest latency for an I/O operation to a single I/O device, the order is of polling, DMA, and interrupt driven.

lowest impact on processor utilization from a single I/O device, the order is DMA, interrupt driven, and polling.

reasons khud likh lain  by comparing 3 techniques in 3-5 lines

Thx B sis

1

2

3

4

5

## Latest Activity

Shaheer Khan, Natasha Maryam and Hammad Atif joined Virtual University of Pakistan
2 minutes ago
6 minutes ago
8 minutes ago
9 minutes ago
10 minutes ago
10 minutes ago
+ !! Ήලᵯᵯℹ Ⲥⱨ !! +!! liked ++❤MQ++A❤❤❤'s discussion tu mila tu mujeh yaqeen aya
12 minutes ago
SAK joined + M.Tariq Malik's group

15 minutes ago