CS501 Current Mid Term Papers Nov 2011, (Fall 2011)

[+ M.Tariq Malik]

Current Mid Term Papers Nov 2011, (Fall 2011)

Current Spring 2011 Papers, May 2011 Papers, Mid Term Spring 2011 Papers, Solved Papers, Solved Past Papers, Solved MCQs

 

[+ M.Tariq Malik]

Please Share your Current Papers Questions/Pattern here to help each other. Thanks

 

[rahila yousaf]

i feel that everyone is mean and don't want to share his/her studies to others.

[fajar]

S501 MIDTERM PAPERS LATEST ALL IN ONE THREAD FALL 2011 MONTH OF MAY

PAPER#1

1. What is relation b/w data path and control unit in SRC processors…….2marks
2. Define Pre-fetching……….2marks
3. Write the structural RTL for “ in ra, rb” ……….3marks
4. What is difference between Latency and Throughput……3marks
5. Write the Structural RTL for “call ra, rb”……….5marks
6. What are the pipeline problems. Describe each briefly…. 5marks

[fajar]

How can you define microprogram? (2 Marks)
A question about to define the shift right instruction? (2 Marks)
What is the utility of reset operation and when it is required? (3 Marks)
Structural RTL instructions definition? (3 Marks)
Write the Structural RTL description for un-conditional jump instruction for
uni-bus data path implementation. (5 Marks)
Define two hazard in pipelining and how can to overcome these. (5 Marks)

[fajar]

Q no 1
Define Control unit. (2 marks)
Q no 2
How can you define Microprogram (2 marks)
Q no 3
Instruction fetch say tha yad nahin (3 marks)
rel Ra
Q no 4
what is the utility of reset operation when it is required (3 marks)

Q no5

what are the types of SRC?Name them? also explain its format? (5 marks)

Q no 6
yad nahin muggar uni- bus say related tha (5 marks)

---

[fajar]

1. How many types of instructions are available in SRC? Name them. What is the format of each of these instructions…….5marks

2. Write the Structural RTL for the call instruction for uni-bus data path implementation.
call ra, rb…………………..5 marks

3. Write the Structural RTL for the mov instruction for uni-bus data path implementation.
mov ra, rb………………………..3 marks

4. How many stages are in the pipelined version of SRC? Name them……..3 marks

5. How can you define microprogram?.....2 marks

6. Write the Structural RTL for the 'not instruction'……….2 marks

[fajar]

Question No: 19 ( Marks: 2 )
How can you define microprogram?
Question No: 20 ( Marks: 3 )
What is the role of timing step generator in a processor?
Question No: 21 ( Marks: 3 )
What is the utility of reset operation and when it is r
Question No: 22 ( Marks: 5 )
Write the Structural RTL description for un-conditional jump
uni-bus data path implementation.
jump [ra+c2]
Question No: 23 ( Marks: 5 )
What function is performed by the reset operation of a processor? What are the
two types of reset operations?
2nd paper
There were 23 questions 1-14 are mcqs others are questions
Q : DEFINE HARD RESET AND SOFT RESET OPERATIONS IN SRC
Q : Write two pipelining problem and define them briefly.
Q : What information is provided by the addressing modes of some processors?
Q : eLEBORATE PRE-FATCHING CONCEPT?
Q : Write RTL functions and there was a rb +rc instruction.
Q : how we speed-up a computer?
Q : Write execution time of an instruction(there was a description too)
Q : Types of instructions
Q : How you represent register data field?

[tlbmst]

mid term fall 2011 on 29-11-11

1. Define pre-fetching. (02 marks)

2. Structural RTL was given and simple syntax was required. (02 marks)  ANSWER   add ra, rb, rc

3. Give strcuctrual RTL of in ra, c2. (03 marks)

4. How exceptions generated? Differentiate between internal and external exceptions. (03 marks)

5. Make structural RTL of shiftr ra, rb, c1 (05 marks)

6. What functions are performed by RESET? Diff b/w hard reset and soft reset. (05 marks)

[+ M.Tariq Malik]

Q1- What is Reset operation describe it types
Q2- Describe super scaler and VILW.
Q3- Write RTL functions and there was a rb +rc instruction
Q4- Write RTL functions and there was a rb +rc instruction
Q5-. Write the structural RTL for “ in ra, rb”

Write the Structural RTL description for un-conditional jump instruction for
uni-bus data path implementation. (5 Marks)

[+ M.Tariq Malik]

My Papers on 27-11-2011.
Total 26 Questions of total 40 Marks.
20 MCQs
6 Short question
All MCQs were from this file compilation.
Control Unit Functionality mention only 3 ,  3 Marks
RTL  Notation.
Define Prefetching.
Jump ra+c2 in RTL notation ,   5 Marks.
Describe to ways to increase the number instruction execution in a
given time .Ecplain one in detail.  ,  5 Mark

[raheel abbasi]

My paper on 29-11-2011

Total 26 Questions and 20 MCQs.

Define Pre-Fetching 2 Mks

Define NOP Instruction 2 MKs

Show the given register in RTL.. 4 question 2 Mks

Structural RTL for unibus In svc 3 Mks

Instruction Fetch using structural RTL

No of ways to increase no of instruction execution in given time

Objective was complete from old papers

Wish you good luck

[+ M.Tariq Malik]

Midterm paper of CS501_Advance Computer Architecture

Campus: VKHI02

Date: 28 November, 2011

 

1. What function is performed by the reset operation of a processor and differentiate Hard reset and Soft reset? [5 marks]

2. Write the Structural RTL for the mov instruction for uni-bus data path implementation.
mov ra, rb [3 marks]

3. Write the Structural RTL  for shift right instruction. [Question was not exactly like that. Every thing was written[i mean structure was already written] we just have to arrange the sequences of the steps.][2 marks only :( ]

4. What is the use of "NOP" instruction in pipelining? [3 marks] 

 

 

 

 

Ask As MCQs.

 

1). LPC: This control signal will enable write of the Program Counter, thus the new,
incremented value can be written into the PC if it is made available on the “in”
bus. Note that the ALSU is assumed to include an INC4 function.

2). Anything that interrupts the normal flow of execution of instructions in the
processor is called an exception.

3).What is the size of the memory space that is available to FALCON-A processor?
Select correct option:
2^8 bytes
2^16 bytes
2^32 bytes
2^64 bytes

 

 

4). What is the working of Processor Status Word (PSW)?
Select correct option:
To hold the current status of the processor.
To hold the address of the current process
To hold the instruction that the computer is currently processing
To hold the address of the next instruction in memory that is to be executed

 

5). What is the instruction length of the FALCON-E processor?
Select correct option:
8 bits
16 bits
32 bits
64 bits

6). Which one of the following portions of an instruction represents the operation to be performed?
Select correct option:
Address
Instruction code
Opcode
Operand

7). Which instruction is used to store register to memory using relative address?
Select correct option:
ld instruction
ldr instruction
lar instruction
str instruction
I don't know its answer but they are from topic: SRC instruction format. 

8). Which type of instructions help in changing the flow of the program as and when required?
Select correct option:
Arithmetic
Control
Data transfer
Floating point

9). A MCQ about Power PC

10). which one of the following is 0-address based machine.

11). There was a very long MCQ not remember now but the options are [this is so strange.]
VCON
FCON
ACON
LCON
I already found all of them keywords on handouts but there is nothing like this.