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CS501 Final Term Papers Spring 2019 (24 August ~ 04 September 2019) & All Solved Past Papers, Solved MCQs & Helping Material

CS501 Final Term Papers Spring 2019 (24 August ~ 04 September 2019) & All Solved Past Papers, Solved MCQs & Helping Material

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Cs501....at 2:30
MCQs is mostly from past papers..
Q1.. Why Flash memory is used in embedded computer??
Q2.. Find avg time give that hit and miss rate..
Q3.. Write code of andi, mul, sub
Q4.. What are interrupts..?

cs501 done..80% mcqs moaz file..5% waqar file..

questions..

what is wirelesstransmission.and discus features

1 numerical tha cpu kitni der me task complete krta ha kuch mbs wgera thi or instruction ..

floating number ky steps thy

multiplication ky way pochy thy

or aik thory qs tha jo yad ni hahah...

Cs501
mcqs almost 15 were from past papers(mega file of moaz)
Questions:
1.What are interrupts? Significance in computer processing?
2.In the context of control unit of cache
TAG RAM
Cache
3.use operators to solve operation - 24*2?
4.Define protocol and host?
4.Three schemes for error control?
5.FALCON-A features?
6.Difference between Computer Organization and Computer Architecture?
7.How does daisy-chain interrupts work?
Baqi yaad nhi.

final paper cs501
mcq
1.a collection of microinstruction is called a microprogram.
2.under-run error ki statment the
3 hardware intrupet ka mcq
4 branc addres
5 intrupet latency
6 the tool loads a FALCON-A binary file with a (.binfa) extension
7 the .equ directive can be used anywhere in the source file to assign values to variables.
8 ard disk m sy platter and tracks k mcq thy
9RAID ka mcq tha aik
10 ALU is a combination of arithmatic
11 flash memory
12 cach ka mcq
13 cache hit ka mcq
14 little law
15 Which one of the following is the memory organization of SRC processor? 2^32 * 8 bits
16 The prior character that was received was not still read by the CPU and is over written by a new received character.
• Framing error
• Parity error
• Overrun error
17 In Multiple Interrupt Line, a number of interrupt lines are provided between the ____________ modules.
• CPU and the I/O (Page 283)
• CPU and Memory
18 The ________ is w-bit wide and contains a data word, directly connected to the data bus which is b-bit wide memory address register (MAR) .
• Instruction Register(IR)
• memory address register (MAR)
• memory Buffer Register(MBR)
19 In a DRAM cell, the storage capacitor will discharge in around ______________ ►4 -15 ms (Page 354)
20 What is the instruction length of the FALCON-E processor? ► 8 bits ► 16 bits ►32 bits
21 Which one of the following instructions is used to load register from memory using a relative address? ►la ►lar ►ldr
22 Taking control of the system bus for a few bus cycles is known as _____________. ►Bus Stealing ►Cycle Stealing (Page 317) ►Cycle Transfering
23 ___________ is the time for first bit of the message to arrive at the receiver including delays. ► Transmission Time ► Latency ► Transport Latency ► Time of Flight
24 __________ is/are defined as the number of instructions processed per second ► Throughput (Page 203) ► Latency Time to process 1 request. ► Throughput and Latency
25 Raid Level ____ is not a true member of the RAID family. ►0 (Page 330) ►2 ►3
###### question
1 feature of connection oriented
2 what is topology and its type
3 overflow of floating point wiyh example
4 branch instruction and addres
5 types of multiplexer detail 5 no ka ? tha
6 radix and diminshed radix complement form
boot recording wala math type ? ta

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