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Graded MDB

Dated: Jan 10, 12

There will be Graded MDB for CS501 on Monday, 16 January, 2012. It will remain open for one day only. The topic for this GMDB is,

 

“Discuss whether variable length instructions are appropriate or not for RISC architecture. Justify your comments with suitable reasons.”

 

A concise, coherent and to the point comment is preferred over lengthy comment having irrelevant details. Your comment must not be more than 7 lines.

 

Comments, posted on regular Lesson's MDB or sent through email will NOT be considered. Any request about such an acceptance will not be catered.


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Replies to This Discussion

Please Discuss here about this GDB.Thanks

“Discuss whether variable length instructions are appropriate or not for RISC architecture. Justify your comments with suitable reasons.”

RISC architectures worked because they enabled
pipelining. They continue to thrive because they enable
parallelism.

Instruction Length

Variable:

Instruction Length

Variable-length instructions (Intel 80x86, VAX) require
multi-step fetch and decode, but allow for a much more
flexible and compact instruction set.
Fixed-length instructions allow easy fetch and decode, and
simplify pipelining and parallelism.

 

 see more for this:

www.sdsc.edu/~allans/cs141/L2.ISA.pdf+variable+length+instructions+..." target="_blank">http://docs.google.com/a/vu.edu.pk/viewer?a=v&q=cache:wbMjVzrEyygJ:www.sdsc.edu/~allans/cs141/L2.ISA.pdf+variable+length+instructions+... 

Usman Ali  gud keep it up 

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