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CS501 Grand Quiz + Mid Term Quiz Fall 2020 Prepartion Material Due Date: 27-12-2020

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CS501 Grand Quiz Fall 2020 (Current Midterm Papers)

CS501 Grand Quiz Fall 2020 | 27-12-2020

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Type D instruction format of SRC includes _________ ALU registers.
Which of the following is not a part of processor state?
For any of the instructions that are a part of the instruction set of the SRC, there are certain ____________ required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
______________ usually involves calculating the target address and evaluating a condition.
MC68000 has a 32-bit program counter but only the least significant __________ bits are used,
In Type C instruction of SRC, the maximum size of constant field is ___________ bits.
Which are the two control unit design approaches?
In SRC, the op-code for NOP operation is ___________ From an n bit control word we may have __________ bit signal values.
Which one of the followings is the correct RTL description for sign extension of a 5-bit constant?
The size of data bus of MC68000 processor is _______.
Below given RTL description belongs to which stage of pipe-lining?
To implement an N-bit barrel shifter in form of a combinational circuit, we require N ___________.
To set the value of micro-PC from branch address, the value of 4 to 1 multiplexer is ______________.
In "Jump [8]" instruction, the size of the constant field is ____________ bits.
In a Falcon-A assembly program, labels are used to implement ____________ jump.

CS501 Grand Quiz Solution Spring 2020
1. ___________ instruction is used to load a register with an immediate data value.
2. In SRC, the memory is accessed in the chunks of __________ byte(s) each. CS501
3. A collection of all possible machine language commands that a computer can understand and execute is called ___________.
4. Which of the following is responsible for generating signals for external events?
5. The size of data bus of MC68000 processor is _______.
6. Which of the following control signals is NOT activated during instruction fetch operation? CS501
7. Upon receiving the ____________ signal, the SRC should perform a hard reset.
8. Which are the two control unit design approaches?
9. In SRC, the general-purpose register file includes ________ registers, each 32 bit wide.
10. Which instruction is used to store register to memory using relative address?
11. The instruction "PUSH A" is an example of ___________.
12. Almost every commercial computer has its own particular __________ language.
13. In FALCON A Program Counter (PC) and Instruction Register (IR) are of _____ bits
14. A __________ is a computer program used to aid in detecting errors in a program.
15. In Structural RTL, the first three time steps (i.e. T0, T1 and T2) are of the instruction ________________ phase.
16. RISC stands for?
17. A __________ is a device that provides a shared data path to a number of devices that are connected to it.
18. In which of the following addressing modes, the address of the memory from where the value is to be accessed is given in the instruction?
19. From an n bit control word we may have __________ bit signal values.
20. Type checking allows the __________ to determine memory requirements for variables.
21. Which one of the following operations is NOT performed by using miscellaneous instructions?
22. Which type of exceptions rise during the process of decoding and executing the instruction?
23. The __________ instruction is completed once memory access has been made and the memory location has been written to.
24. ________ is an example of Miscellaneous instruction.
25. The Memory Buffer Register (MBR) has a ___________ connection with both the memory sub-system and the registers/ALSU.
26. In Falcon-A ISA, which of the following opcodes is used to perform "No Operation"?
27. In "Jump [8]" instruction, the size of the constant field is ____________ bits.
28. “If P = 1, then load the contents of register R1 into register R2”. This statement can be written in RTL as:
29. Which of the following notations represents the indexed or scaled addressing mode in any processor?
30. ________ controls the sequence of the flow of microinstructions.

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CS501 Grand Quiz Solution Spring 2020

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