CS501 Please share your current paper here 11/5/2012 to 22/5/2012

[Sana Sunny ツ]

Please share your current paper here for help each other.

Stay blessed and Best of Luck for exam.

Remember me in your prayers.

Best Regards,

sana

[Sana Sunny ツ]

Please share your current paper here for help each other.

Stay blessed and Best of Luck for exam.

Remember me in your prayers.

Best Regards,

sana

[syeda Areeba]

1. Which registers hold the instructions that is being executed?(2 Marks)
2. What do you understand by the machine exceptions?(2 Marks)
3. Write the structural RTL for the mov immediate instruction for the mov immediate instruction for uni-bus data path implementation

Movi ra,c2 (3marks)

4.What is NOP instruction and its significance in pipelining? (3 Makrs)

5.Consider the following sequence of the instructions giving through the pipelined version of SRC

200:shl r6,r3,5

204:str r7,30

208:sub r2,r4,r5

2012:add r1,r2,r3

216:id r7,48

Idetify the hazards in these instructions. Also discuss how hazards be resolved (5 marks)

6.Write the structure RTL description for the uni-bus data path implementation

Jump[ra+2] (5 Marks)  

[saima007]

My current midterm paper CS501 19/05/2012

80% mcq form past papers and quizzes 20 % new mcq.

Subjective Question:

Q1. Which register holds the address of the next instruction to b executed in the processor?    (2 Marks)

Q2. What do you know about Machine Exception? (2 Marks)

Q3. How exception may b generated write the difference between external and internal exceptions?   (3marks)

Q4. Write the structure RTL description for mov instruction (3 Marks)

Q5. Write the structure RTL description for shift instruction? (5 Marks)

Q6. Identify Hazard in the instructions and resolve it? (5 Marks)

[NaumanX2]

Almost 70% MCQ's was from old Papers and quiz's

Subjective Part

Q -   Write a structural RTL for Shift instruction for Uni-Bus data path implementation.      

     shiftr ra, rb, c1      [5 Marks]                                                                                          

Q -  One Structural RTL Table was given, you have to tell the simple Equation and what it for?   [5 Marks]

Q -  Write down one Advantage and Disadvantage of Microprogramming?   [3 Marks]

Q -  Difference between Memory Address Register and Memory Buffer Register?   [2 Marks]

Q -  4-5 instructions were given and asked the pipe-lining hazards in it also correct it.?  [2 Marks]

All the Best

[Syed M. Umair Saulat]

MID TERM Paper

Dated May 11,2012

Time 1 hour

Attempt by On Sara Aman Sara Aman" <[e-mail]>, May 11, 2012 at 2:14 PM,

 

Which register holds the address of the next instruction to b executed in the processor?         2 marks

Answer:

PC holds the address of next instruction to b executed in the processor.

Write the main functions of the branch instruction?     2 marks

Answer:

1)      calculate the target address

2)      to evolutes the condition

Write the structural RTL for the following instruction for the uni- bus  path implementation? in ra,rc          3 marks

Answer:

 

steps	RTL
T0-T2	Instruction fetch
T3	C  io[2]
T4	R[ra]C

 

How exception may b generated write the difference between external and internal exceptions?     3 marks

Answer:

 

Anything that interrupts the normal flow of execution of instructions in the

processor is called an exception.

• Exceptions may be generated by an external or internal event such as a mouse

click or an attempt to divide by zero etc.

• External exceptions or interrupts are generally asynchronous (do not depend on

the system clock) while internal exceptions are synchronous (paced by internal clock.

 

Write the two ways to increase the number of instruction in a given time by the processor? Explain each one briefly?  5 marks

 

Answer:

 

There are two ways to increase the number of instructions executed in a given time by a

processor

By increasing the clock speed

By increasing the number of instructions that can execute in parallel

Increasing the clock speed

• Increasing the clock speed is an IC design issue and depends on the advancements in

chip technology.

• The computer architect or logic designer can not thus manipulate clock speeds to

increase the throughput of the processor.

Increasing parallel execution of instructions

The computer architect cannot increase the clock speed of a microprocessor however

he/she can increase the number of instructions processed per unit time. In pipelining we

discussed that a number of instructions are executed in a staggered fashion, i.e. various

instructions are simultaneously executing in different segments of the pipeline. Taking

this concept a step further we have multiple data paths hence multiple pipelines can

execute simultaneously.

 

Write the structural RTL for the call instruction for the uni data path implementation?

Call ra, rab

Answer:

 

 

steps	RTL
T0-T2	Instruction fetch
T3	C PC
T4 T5 T6	R[ra] C CR[rb] PCC

[+ M.Tariq Malik]

aoa, all
my todays' paper was so easy,
mcq's handouts me se ay thay sirf kuch he past papers se ay thay
other questios were
What is function of machine reset?, difference between hard and soft reset? 5
ek RTL jump instruction ai thi 5 marks ka
short questions was so easy
internal and external exception 2
i just prepared first 8 and last 7 lectures.. 

[M saqib khan]

Mcqs are very easy..

1- two approaches for control unit.

2- what is microprogram.

3- structural RTL for mov ra, rb

4- structural RTL and explaination for instruction fetch.

5- find out the hazard from the instructions given .. same like are in handouts.

[+ M.Tariq Malik]

CS501 today paper by Safeena Ali

See the attached file 

[+ M.Tariq Malik]

CS501     today paper

Date 13-05-2012

What is the instruction length of the FALCON-E processor?
Select correct option:
8 bits
16 bits
32 bits
64 bits

Which one of the following circuit design levels is called the gate level?
Select correct option:
Logic Design Level
Circuit Level
Mask Level
None of the given

 

What does the word ‘D’ in the ‘D-flip-Flop’ stands for?
Select correct option:
Data
Digital
Dynamic
Double

The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
Select correct option:
Add R3, 56
lar R3, 56
ldr R3, 56
str R3, 56

 

Which instruction is used to store register to memory using relative address?
Select correct option:
ld instruction
ldr instruction
lar instruction
str instruction

Which one of the following registers holds the instruction that is being executed?
Select correct option:
Accumulator
Address Mask
Instruction Register
Program Counter

For any of the instructions that are a part of the instruction set of the SRC, there are certain ____________ required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
Select correct option:
Registers
Control signals
Memory
None of the given

www.vustudents.ning.com

The external interface of FALCON-A consists of a ________ data bus.
Select correct option:
8-bit
16-bit
24-bit
32-bit

__________ enable the input to the PC for receiving a value that is currently on the internal processor bus.
Select correct option:
LPC
INC4
LC
Cout

Which one of the following register(s) that is/are programmer invisible and is/are required to hold an operand or result value while the bus is busy transmitting some other value?
Select correct option:
Instruction Register
Memory address register
Memory Buffer Register
Registers A and C

 

-------------- performs the data operations as commanded by the program instructions.
Select correct option:
Control
Datapath
Structural RTL
Timing

www.vustudents.ning.com

 

 

Question:-

Write down two processors name of superscalar architecture  mark 2

Question:-

Convert table into instruction form

Question:-

How exception may b generated write the difference between external and internal exceptions?  3 marks          

           

Question:-

What are the pipeline problems. Describe each briefly…. 5marks

Question:-

Write the structure RTL description for the uni-bus data path implementation

Jump[ra+2] (5 Marks)

 

[preety]

Which registers hold the instructions that is being executed?

Structural RTL for instruction fetching

What is the role of time step generator?

What are pipelining problems?Describe each briefly.

Diff b\w microprograme and hardwired control unit?

[+ M.Tariq Malik]

preety  thanks for sharing paper to help other .keep it up 

[+ M.Tariq Malik]

CS 501 Solved Subjective Questions for Mid Term Mega File