CS501 Spring 2018 Final Term Papers Pattern & Questions 01 September 2018 to 12 September 2018 & Helping Material

[+ M.Tariq Malik]

CS501 Spring 2018 Final Term Papers Pattern & Questions 01 September 2018 to 12 September 2018 & Helping Material

[+ M.Tariq Malik]

Share Your Final Term Papers (Questions/Pattern) & Past Papers as well here to help each other. Thanks

 

Note:-

For Important Helping Material related to this subject (Solved MCQs, Short Notes, Solved past Papers, E-Books, FAQ,Short Questions Answers & more). You must view all the featured Discussion in this subject group.

For how you can view all the Featured discussions click on the Back to Subject Name Discussions link below the title of this Discussion & then under featured Discussion corner click on the view all link.

Or visit this link 

 

Click Here For Detail.

&

 

.•°How to Download past papers from study groups°•.

 

Please Click on the below link to see…

.... How to Find Your Subject Study Group & Join .... 

 

[+ M.Tariq Malik]

Final term Solved Mooaz Past Papers

Final Term Solved Papers Mega Files link

Pas papers Solved final term By Waqar

Final Term Past papers Solved By Moaaz

Final term Solved Mooaz Past Papers

Final Term Solved Papers Mega Files link

Pas papers Solved final term By Waqar

Final Term Past papers Solved By Moaaz

 

Share your Helping material related this subject here to help each other. Thanks

[+!!++ ZIA ASAD (BSCS-7) +++++]

a o a

Today my paper 

34 approx mcqs were from waqar file and 

max subjective from moiz file

daisy chain etc.

[+ M.Tariq Malik]

ZIA ASAD (BSCS-6)  thanks for sharing 

[+ M.Tariq Malik]

Today cs501 current paper

 

1)write the general sequence of steps involved in interrupt handling?

 

2)give a brief overview of the different types of instruction formats of FALCON_A?

 

3)consider a 32KB direct-mapped cache with a length of 16bytes

 

a)determine the number of bits in the address that refers to the byte with in a cache line.

 

b)determine the number of bits in the address required to select the cache line.

 

4)how many inputs and outputs are available in one level decoder? Also describe the usage of matrix decoders?

 

5)Differentiate between even parity and odd parity?

 

6)what happen when a microprocessor is interrupted?

 

7)what does following field of SRC instruction represent 

 

IR<31……O>

 

8)explain the steps which are involved in transferring the data using DMA?

 

9)4 way set
256KB capacity and 32 byte lines?
a)how many sets are there in the cache.
b)how many bits of address are required to select a set in cache.

[Mrs Asad Aleem]

why me cant able to get wqar file...........................