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I am uploading CS501 MCQs Moaz File with corrections, See the uploaded file In some questions Corrected Answer Choice is marked with Yellow highlight.

Best Of Luck...!

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CS501 today's paper

mcq past past paper.20 marks
1.differenc b/w external nd internal interupt by the sysytem clock? 2 marks
2. how compiler solution to hazards? 2 marks
3. data hazard detection and correction? 3 marks 
4. roll of timer generator in the processor. 3 marks
5. structural RTL for fetch instruction? 5 marks 
6. Detect the hazard in the given instruction and then resolved them? 5 marks
200: shl r6, r3, 2
204: str r3, 32
208: sub r2, r4,r5
212: add r1,r2,r3
216: ld r7

Sb keh ry easy paper easy paper mtlb Pehly pehly papers easy aa gye ab mushkl ki baari hamaari dafa 

all paper  frome mozz fil subjective and object 

1)resaet opration names

2)

Detect the hazard in the given instruction and then resolved them? 5 marks

200:  shl  r6, r3, 2

204:  str r3, 32

208:  sub r2, r4,r5

212:  add r1,r2,r3

216:  ld r7, 48

3)Define RTL description of Shiftr ra,rb,c1? 5 marks

4)RTL given and identfy and chnage into assembly .

ans"sub RTL

5)difference latency and throughtput

6)Define RTL description of Mov  ra,rb ?

please answer this question, whoever knows this. it is urgent

still waiting for the answer of above question

asslam o alikm dear students mje b cs 501 ka paper past me se hi aya hai .so plzzz moaz ki objective and subjective uni k pprs me se aa rahi hai wo achi tra kr lein bs mcqz 3,4 new the baki past me se hi ata hai.over all ppr bohat eas tha .remember me in ur prayers.thanksss

thanks 

Ab pta ni mra paper ksa ho ga  mj is ka kch ni ata totaly nill i m  plz pray 

My paper...!

Attachments:

My Today’s paper CS501 5 June 2013

Note: (Overall paper was from past paper + current papers. 2-3 mcqs were new and one 5 marks question was new)

MCQS:

 

  1. FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC _____wide. ►8-bits ►16-bits ►32-bits (Page 157) ►64-bits

 

  1. _________control signals enable the input to the PC for receiving a value that is currently on the internal processor bus. ►LPC (Page 172) ►INC4 ►LC ►I

 

  1. _______ operation is required to change the processor‟s state to a known, defined value. ►Change ►Reset (Page 194) ►Update ►None of the given

 

  1. Which one of the following is a bi-stable device, capable of storing one bit of information? ►Decoder ►Flip-Flop (Page 76) ►Multiplexer ►Diplexer

 

  1. The external interface of FALCON-A consists of a ______address bus and ______a data bus. ►8-bit. 8-bit

►16-bit. 16-bit Click here for detail ►16-bit. 24-bit ►16-bit. 32-bit

 

  1. What is the instruction length of the SRC processor? ► 8 bits ► 16 bits ► 32 bits (Page 134) ► 64 bits
  2. P: R3 ¬ R5 MAR ¬ IR These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously? ► Arrow ¬ ► Colon : ► Comma , (Page 69) ► Parentheses ()

 

  1. Prefetching can be considered a primitive form of------------- ►Pipelining (Page 42) ►Multi-processing ►Self-execution ►Exception

 

 

  1. There are _________ types of reset operations in SRC ► Two (Page 195) ► Three ► Four ► Five

 

  1. What is the working of Processor Status Word (PSW)? ►To hold the current status of the processor. (Page 28) ►To hold the address of the current process ►To hold the instruction that the computer is currently processing ►To hold the address of the next instruction in memory that is to be executed

 

 

  1. Almost every commercial computer has its own particular ---------- language ►3GL ►English language ►Higher level language ►assembly language

 

  1. Which of the instruction is used to load register from memory using a relative address? ►ld instruction ►ldr instruction (Page 47) ►lar instruction ►str instruction

 

 

  1. Which one of the following portions of an instruction represents the operation to be performed? ►Address ►Instruction code ►Opcode ►Operand

 

  1. Which one of the following registers holds the address of the next instruction to be executed?

           

Accumulator
Address Mask
Instruction Register
Program Counter

  1. Which one of the following circuit design levels is called the gate level?
    Select correct option:

    Logic Design Level
    Circuit Level
    Mask Level
    None of the given

 

  1. For any of the instructions that are a part of the instruction set of the SRC, there are certain ____________ required; which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
    Select correct option:

    Registers
    Control signals
    Memory
    None of the given

 

 

  1. Which type of instructions load data from memory into registers, or store data from registers into memory and transfer data between different kinds of special-purpose registers? 

 

Select correct option: 

Arithmetic

Control

 Data transfer

 Floating point

 Subjective paper:

 

  1. 1.      What function is performed by the reset operation of a processor?    2 marks

Answer:- (Page 194)

Reset operation is required to change the processor’s state to a known, defined value. The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value.

 

  1. What is relation b/w data path and control unit in SRC processors?     2 marks

Answer:- (Page 186)

By means of the control signals, the control unit instructs the data path what to do in every clock cycle during the execution of instructions.

 

  1. Describe three main functions of control unit.     3 marks

Answer:-

• It carries out many tasks such as decoding, fetching, handling the execution and finally storing the results.

• It interprets the instructions.

• It regulates the time controls of the processor

 

  1. Write the structural RTL for the mov instruction for the uni data path implementation?  mov ra, rb                                 3 marks

Answer:- (Page 164)

 

 

 

 

  1. Write the structural RTL for the call instruction for the uni data path implementation?

Call ra, rb                                 5 marks

Answer:- (Page 165)

 

 

 

 

  1. 6.      Data dependency is a cause of hazards in pipelining. What are the different techniques used to resolve data dependency?  5 marks

Pipeline stalls

Consider the following sequence of instructions going through the SRC pipeline

200: shl r6, r3, 2

204: str r3, 32

208: sub r2, r4,r5

212: add r1,r2,r3

216: ld r7, 48

There is a data hazard between instruction three and four that can be resolved by using pipeline stalls or bubbles

When using pipeline stalls, nop instructions are placed in between dependent instructions.

The logic behind this scheme is that if opcode in stage 2 and 3 are both alu, and if ra in stage 3 is the same as rb or rc in stage 2, then a pause signal is issued to insert a bubble between stage 3 and 2. Similar logic is used for detecting hazards between stage 2 and 4 and stage 4 and 5.

Data Forwarding

By adding data forwarding mechanism to the SRC data path, the stalls can be completely eliminated at least for the ALU instructions. The hazard detection is required between stages 3 and 4, and between stages 3 and 5. The testing and forwarding circuits employ wider IRs to store the data required in later stages. The logic behind this method is that if the ALU is activated for both 3 and 5 and ra in 5 is the same as rb in 3 then Z5 which hold the currently loaded or calculated result is directly forwarded to X3. Similarly, if both are ALU operations and instruction in stage 3 does not employ immediate operands then value of Z5 is transferred to Y3. Similar logic is used to forward data between stage 3 and 4.

 

Control signal allows the bus to read from the selected register

  • RBE
  • RCE
  • LCON
  • R2BUS

 

Jump is which type of instruction

  • Data transfer
  • Control instruction
  • Arithmetic instruction
  • None of the above

 

Addressing mode, data is part of the instruction, no need of addressing.

  • Direct Addressing Mode
  • Immediate addressing mode
  • Indirect Addressing Mode
  • Register (Direct) Addressing Mode

new mcqs other thn moaaz file jo meray paper mai aye thy.

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