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CS501 - Advance Computer Architecture GDB No. 1 Solution Fall 2015 Due Date: Tuesday, February 16, 2016
Graded Discussion Board (GDB) will be launched on Monday, February 15, 2016 and it will close on Tuesday, February 16, 2016.
Pipelining is a popular technique widely used in computer architecture that provides the support of instruction parallelism. Suppose that, five different instructions are going to be executed at different stages of the pipeline, e.g. stage 1 have one instruction, stage 2 have other instruction and so on. Further, assume that, these instructions can execute in parallel at different stages of the pipeline and the size of instructions can vary.
Keeping in view the dependency and the size of each instruction from the above scenario, which instruction will execute first from the different stages of pipelining given below?
Stage 1: Instruction fetch -> Instruction 1
Stage 2: Instruction decode -> Instruction 2
Stage 3: ALU operation -> Instruction 3
Stage 4: Memory access -> Instruction 4
Stage 5: Register write -> Instruction 5
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In this lecture, a pipelined version of the SRC is presented. The SRC uses a five-stage
pipeline. Those five stages are given below:
1. Instruction Fetch
2. Instruction decode/operand fetch
3. ALU operation
4. Memory access
5. Register write
After the instruction has been fetched, it is stored in IR2 and the incremented value of the
program counter is held in PC2. When the register values have been read, the first
register value is stored in X3, and the second register value is stored in Y3. IR3 holds the
opcode and ra. If it is a store to memory instruction, MD3 holds the register value to be
Adapting SRC Instructions for Pipelined Execution
As mentioned earlier, the SRC instructions fall into the following three categories:
1. ALU Instructions
2. Load/Store instructions
3. Branch Instructions
We will now discuss how to design a common pipeline for all three categories of
1. ALU instructions
ALU instructions are usually of the form:
op-code ra, rb, rc
op-code ra, rb, constant.
In the diagram shown, X3 and Y3 are temporary registers to hold the values between
pipeline stages. X3 is loaded with operand value from the register file. Y3 is loaded with
either a register value from the register file or a constant from the instruction. The
operands are then available to the ALU. The ALU function is determined by decoding the
op-code bits. The result of the ALU operation is stored in register Z4, and then stored in
the destination register in the register write back stage. There is no activity in the memory
access stage for ALU instructions. Note that Z5, IR3, IR4, and IR5 are not shown
explicitly in the figure. The purpose of not including these registers is to keep the
drawing simple. However, these registers will transfer values as instructions progress
through the pipeline. This comment also applies to some other figures in this discussion.
2. Load/Store instructions
Load/Store instructions are usually of the form:
op-code ra, constant(rb)
The instruction is loaded into IR2 and the incremented value of the PC is loaded in PC2.
In the next stage, X3 is loaded with the value in PC2 if the relative addressing mode is
used, or the value in rb if the displacement addressing mode is used. Similarly, C1 is
transferred to Y3 for the relative addressing mode, and c2 is transferred to Y3 for the
displacement addressing mode. The store instruction is completed once memory access
has been made and the memory location has been written to. The load instruction is
completed once the loaded value is transferred back to the register file. The following
figure shows the schematic for a load instruction. A similar schematic can be drawn for
the store instruction.
3. Branch Instructions
Branch Instructions usually involve calculating the target address and evaluating a
condition. The condition is evaluated based on the c2 field of the IR and by using the
value in R[rc]. If the condition is true, the PC is loaded with the value in R[rb], otherwise
it is incremented by 4 as usual. The following figure shows these details.
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Pipelining increases instruction throughput by performing multiple operations at the same time, but does not reduce instruction latency, which is the time to complete a single instruction from start to finish, as it still must go through all steps. Indeed, it may increase latency due to additional overhead from breaking the computation into separate steps and worse, the pipeline may stall (or even need to be flushed), further increasing the latency. Thus, pipelining increases throughput at the cost of latency, and is frequently used in CPUs but avoided in real-time systems, in which latency is a hard constraint.
Each instruction is split into a sequence of dependent steps. The first step is always to fetch the instruction from memory; the final step is usually writing the results of the instruction to processor registers or to memory. Pipelining seeks to let the processor work on as many instructions as there are dependent steps, just as an assembly linebuilds many vehicles at once, rather than waiting until one vehicle has passed through the line before admitting the next one. Just as the goal of the assembly line is to keep each assembler productive at all times, pipelining seeks to keep every portion of the processor busy with some instruction. Pipelining lets the computer's cycle time be the time of the slowest step, and ideally lets one instruction complete in every cycle.
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