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Graded Discussion Board (GDB) will be launched on Wednesday, August 10, 2016 and it will close on Thursday, August 11, 2016.

Graded Discussion Board (GDB) Dated: Aug 03, 16

Dear Students!

Graded Discussion Board (GDB) will be launched on Wednesday, August 10, 2016 and it will close on Thursday, August 11, 2016.

 

GDB Topic:

Suppose an I/O device needs to gain access from the system memory in order to transfer or exchange data to and from the memory. There are different types of data and it can be text, image, graphics or multimedia data including audio or video. There can be large amount of data transfer between device and memory along with the light amount of data. During transferring large amount of data, the system will take extra time and system resources; it may cause other running applications to slow down as well. Keeping in view the performance and timing characteristics, which technique would be more suitable for the speedy transfer of data and smoothly running of other system applications?

You are required to mention one technique and justify your answer with solid reasons.

Instructions:

Justify your answer with valid reasons and refrain from cheating material/links. Try to provide precise, to the point answer and avoid irrelevant details.

For any query: CS501@vu.edu.pk

Instructor CS501


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Please Discuss here about this GDB.Thanks
Our main purpose here discussion not just Solution
We are here with you hands in hands to facilitate your learning and do not appreciate the idea of copying or replicating solutions.

Dear Students Don’t wait for solution post your problems here and discuss ... after discussion a perfect solution will come in a result. So, Start it now, replies here give your comments according to your knowledge and understandings....

Device wishing to perform DMA asserts the processors bus request signal.
Processor completes the current bus cycle and then asserts the bus grant signal to the device.
The device then asserts the bus grant ack signal.
The processor senses in the change in the state of bus grant ack signal and starts listening to the data and address bus for DMA activity.
The DMA device performs the transfer from the source to destination address.
During these transfers, the processor monitors the addresses on the bus and checks if any location modified during DMA operations is cached in the processor. If the processor detects a cached address on the bus, it can take one of the two actions:
Processor invalidates the internal cache entry for the address involved in DMA write operation
Processor updates the internal cache when a DMA write is detected
Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal.
Processor acknowledges the bus release and resumes its bus cycles from the point it left off.

DMA channels are used to communicate data between the peripheral device and the system memory. All four system resources rely on certain lines on a bus. Some lines on the bus are used for IRQs, some for addresses (the I/O addresses and the memory address) and some for DMA channels.

A DMA channel enables a device to transfer data without exposing the CPU to a work overload. Without the DMA channels, the CPU copies every piece of data using a peripheral bus from the I/O device. Using a peripheral bus occupies the CPU during the read/write process and does not allow other work to be performed until the operation is completed.

With DMA, the CPU can process other tasks while data transfer is being performed. The transfer of data is first initiated by the CPU. During the transfer of data between the DMA channel and I/O device, the CPU performs other tasks. When the data transfer is complete, the CPU receives an interrupt request from the DMA controller.

A device applying DMA technology uses only a single channel. To avoid a conflict, sometimes the BIOS must assign a different channel to a device. A conflict can happen when more than one device tries to use the same channel.

DMA channels are slower than later data transfer methods, and therefore are not as common. One later interface is the Ultra DMA, which has a data transfer rate up to 33 MB per second. Each DMA transfers approximately 2 MB data per second.

uring any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave. The CPU with its bus control logic is normally the master, but other specially designed components can gain control of the bus by sending a bus request to the CPU. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master.

Taking control of the bus for a bus cycle is called cycle stealing. Just like the bus control logic, a master must be capable of placing addresses on the address bus and directing the bus activity during a bus cycle. The components capable of becoming masters are processors (and their bus control logic) and DMA controllers. Sometimes a DMA controller is associated with a single interface, but they are often designed to accommodate more than one interface.

The 8086 microprocessor receives bus requests through its HOLD pin and issues grants from the hold acknowledge (HLDA) pin. A request is made when a potential master sends a 1 to the HOLD pin. Normally, after the current bus cycle is complete the 8086 will respond by putting a 1 on the HLDA pin. When the requesting device receives this grant signal it becomes the master. It will remain master until it drops the signal to the HOLD pin, at which time the 8086 will drop the grant on the HLDA pin. One exception to the normal sequence is that if a word, which begins at an odd address is being accessed, then two bus cycles are required to complete the transfer and a grant will not be issued until after the second bus cycle.

When a DMA controller becomes master it places an address on the address bus and sends the interface the necessary signals to cause it to put data on, or receive data from, the data bus. Since the DMA controller determines when the bus request is dropped, it can return control to the CPU after each data byte is transferred and then request control again when the next data byte is ready, or it can retain control until the entire block is moved. The former is the usual case because this allows the CPU to continue its work until the next data byte is available.

Sahrish ap k 2 replies hain... kya 2nd wala continued me he ya seperate he 1st se? and if seperated than what is correct one?

ya GDB kis chapter main sa aya ha

DMA is a feature of computer systems that allows certain hardware subsystems to access main system memory independently of the CPU. DMA means CPU grants I/O module authority to read from or write to memory without involvement. In short It can transfer data directly to and from memory. With DMA, the CPU first initiates the transfer, and then it does other operations while the transfer is in progress, and it finally receives an interrupt from the DMA controller when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer.

DMA is much useful when a large amount of data needs to be transferred with a good speed. Many hardware systems use DMA, including disk drive controllers, graphic, network and sound cards. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels. Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time allowing computation and data transfer to proceed in parallel. DMA can also be used for memory to memory copying or moving of data within memory. 

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