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MCSQS  32 from mooaz file

Subjective some from mooaz file now all the subjective come from this i have also done ?

Q: Can the DMA controller Direct to Access Virtual Memory ? 2 marks

Answer:- A DMA controller could be a CPU in itself and it could control the total  activity  and  synchronize  the  transfer  of  data but  the DMA controller knows nothing of virtual memory, it only has access to the physical memory in the system.


Q: What does its Mean when Represent some Number In sign magnitude form? 2 marks

Answer: To represent a number in sign-magnitude, we simply use the leftmost bit to represent the sign, where 0 means positive, and the remaining bits to represent the magnitude (total value).


Tram Fragmentation in computer network? Not in Current Papers  2 marks


When a packet is lost in the network, it is re-transmitted. If the size of the packet is large then retransmission of packet is wastage of resources and it also increases the delay in the network.  To  minimize  this  delay,  a  large  packet  is  divided  into  small  fragments.  Each fragment  contains  a  separate  header  having  destination  address  and  fragment  number.

This fragmentation effectively reduces the queuing delay.


Q: Describe Tram Polling In Reference To Programming I/O?  2 marks

Interrupt driven I/O is better than polling, In the case of polling a lot of time is wasted in

questioning the peripheral device whether it is ready for delivering the data or not.


Although  different  techniques  have  been  used  to  increase  the  efficiency  of  the

programmed I/O, overheads due to polling can not be completely eliminated.


Q:- What is the use of translation Lookside buffer(TLB) and How it is implemented inside the  2U? 3 marks

Answer:- Identifying a particular page in the virtual memory requires page tables  resulting in large memory  space to implement these page tables.

To speed up the process of virtual address translation, translation Lookaside buffer (TLB) is implemented as a small cache inside the CPU, which stores the most recent page table entry reference made in the MMU.


Q:- the basic scheme which are used for synchronization of I/O data transmission?  3 marks

There  are  three  basic  schemes  which  can  be  used  for  synchronization  of  an  I/O  data


=  Synchronous transmission

=  Semi-synchronous transmission

=  Asynchronous transmission


Q: Briefly explain  arguments of block in a 1X8 memory cell array(1D)?3 marks

In  this  arrangement,  each  block  is  connected  through  a  bi-directional  data  bus implemented  with  2  tri-state  buffers. R/W and  Select  signals  are  common  to  all  these

cells. This 1-dimensional memory array could not be very efficient, if we need to have a

very large memory. 


Q:- explain the steps  which are involved transferring the data using DMA? 5 Marks

Answer:- Data transfer using DMA takes place in three steps.


Step 1:-

in  this  step  when  the  processor  has  to  transfer  data  it  issues  a  command  to  the  DMA

controller with the following information:

 Operation to be performed i.e., read or write operation.

  Address of I/O device.

  Address of memory block.

  Size of data to be transferred.


2nd step:-

In this step the entire block of data is transferred directly to or from memory by the DMA



3rd step:-

In this, at the end of the transfer,  the DMA controller informs the processor by sending an interrupt signals?


Q:- suppose an I/O system with a single Disk gets 200 I/O request/s, and the average time for a disk to revise  an  I/O requests in 4-ms. What is the utilization of I/O system?


Answer:-  Time for the I/O request = 4

                                                             = 0.004sec

                   Server utilization = 200 x 0.004

                                                          = 0.4


pipeline instruction increase what? Throughput or latency.  2 marks


Throughput increase the pipeline instruction process (throughput is defined as the number of instructions processed per second)Instruction pipelining means having multiple instructions in different stages of execution as  instructions  are  issued  before  the  previous  instruction  has  completed  its  execution;


Which type of interrupt applied to the pin of the processor ? 2marks

Answer:- Maskable Interrupts: - These interrupts are applied to the INTR pin of the processor.


Q:- is the branch address of the interrupt service routine is fixed , identity ?

In  non-vectored  interrupts,  the  branch  address  of  the  interrupt  service  routine  is  fixed.  

Q:- define overflow condition ?

Answer In  computers,  a  floating-point  number ranges from 1.2 × 10-38 ≤ x ≤ 3.4 × 1038 can be represented. If a number does not lie in this range, then overflow can occur Overflow  occurs  when  the  exponent  is  too  large  and  can  not   be  represented  in  the exponent field.


Q:- difference and similarity B/W RAID 4,5?

RAID Level 4

•  Make use of independent access technique.

•  Data striping is used.

•  A bit-by-bit parity strip is calculated across corresponding strip on each data disk.

RAID Level 5

•  Organized in a similar fashion to RAID 4

•  The only difference is that RAID 5 distributes the parity strips across all disks.


How many platters are required for a 40GB disk if there are 1024 bytes/sector, 2048 sectors per track and 4096 tracks per platter



The capacity of one platter= 1024 x 2048 x 4096

= 8GB

For a 40GB hard disk, we need 40/8

= 5 such platters.


Q :-Define  PROM ?

The PROM stands for Programmable Read only Memory. It is also nonvolatile and may

be written into only once. For PROM, the writing process is performed electrically in the

field. PROMs provide flexibility and convenience.


Advantages of interrupts:

•  Useful for interfacing I/O devices with low data transfer rates.

•  CPU is not joined up in a fixed loop for polling the I/O device.


how many minimum devices do you need to from RAID 0?

To establish a RAID 0 volume, a minimum of at least 2 hard disk drives are required. Unlike RAID 1, the number of drives used in the array can be an odd or even number.


Q:- using Shift operation , multiply given numbers -24X2?



-24= (101000)2

-24x2= (010100)2 = 20

-24x2= (110100)2= -12

Changing the size of the number,

24= 011000 (n=6) to 00011000 (n=8)

-24= 101000 (n=6) to 11101000 (n=8)


keeping the cache memory management into view ,explain? Write through Write back

Write  Through:  As  the  data  is  written  into  the  cache,  it  is  also  written  into  the  main

memory called Write Through.

Write Back:  Date exist in  the cache, till we need to replace a particular block then the

data of that particular block will be written into the memory if that needs a write, called

write back.


Q:-write the different mechanisms that can be used to avoid the device identification 
design issue with respect to interrupt handling?

In this issue different mechanisms could be used.

Multiple interrupt lines

This  is  the  most  straight  forward  approach,  and  in  this  method,  a  number  of  interrupt

lines are provided between the CPU and the  I/O module.

Software Poll

CPU polls to identify the interrupting module and branches to an interrupt service routine

on detecting an interrupt.

Daisy Chain

The wired or interrupt  signal allows several devices to request interrupt simultaneously.

what is the use of .org directive in falsim? 2 marks

The  .org  directive can also be used anywhere in the source file to force code at a particular address in the memory.


Explain static property of hard disk? 3mrks

Hard Disk

Peripheral devices connect the outside world with the central processing unit through the

I/O modules. One important feature of these peripheral devices is the variable data rate.

Peripheral devices are important because of the function they perform.

A hard disk is the most frequently used peripheral device. It consists of a set of platters.

Each platter is divided into tracks. The track is subdivided into sectors. To identify each

sector, we need to have an address. So, before the actual data, there is a  header and this

header consisting of few bytes like 10 bytes. Along with header there is a trailer. Every

sector has three parts: a header, data section and a trailer.

Static Properties

The storage capacity can be determined from the number of platters  and the number of

tracks. In order to keep the density same for the entire surface, the trend is to use more

number of sectors for outer tracks and lesser number of sectors for inner tracks.


what is DRam and it cell fuctionality?3mrks

In a DRAM cell, the storage capacitor will discharge in around 4 -15ms. Refreshing the

capacitor by reading or sensing the value on bit line, amplifying it, and placing it back on

to the bit line is required.


write names of 3 control signals and explain any 2? 5

LMBR  is  the  control  signal  to  enable  write  of  the  MBR  (Memory  Buffer  Register).  It

will obtain its value from the CPU external data bus.

MBRout  is the control signal to allow the contents of the MBR to be read out onto the

CPU internal bus.

PCout: This control signal allows the contents of the Program Counter register to be

written onto the internal processor bus.


Q:- which I/O technique  refer  the situation when all I/O operations are performed under the

direct control of a program running on the CPU.

Programmed I/O.



What are the sectors on the hard disk?
A hard disk is the most frequently used peripheral device. It consists of a set of platters.

Each platter is divided into tracks. The track is subdivided into sectors. To identify each

sector, we need to have an address. very sector has three parts: a header, data section and a trailer.


Write one advantage and one disadvantage direct mapped cache.




Only  a  single  block  from  a  given  group  is  present  in  cache  at  any  time.  Direct

map Cache imposes a significant amount of rigidity on cache organization.


How does the Daisy-Chain priority interrupts method works?

•  The devices interrupt the CPU.

•  The CPU sends acknowledgement to the maximum priority device.

•  If  the  interrupt  was  generated  by  the  device,  the  interrupt  for  the  device  is


•  Otherwise the acknowledgement is passed to the next device.


Q:-Identify and explain the working of the given DMA configuration.

DMA Configurations:

•  Single Bus Detached DMA

•  Single Bus Integrated DMA

•  I/O Bus


Find out the sign, significant and exponent from the following floating point number.-06 x 10^-3?

Answer:-  sign = -1

Significand = 6

Exponent= -3

Base = 10= fixed for given type of representation


Briefly explain the two types of hardware interrupts.

Hardware interrupts are generated by the external hardware.

Software interrupts are generated by the software using some interrupt instruction

Hardware interrupts: -

Hardware interrupts are generated by external events specific to peripheral devices. Most

processors have at least one line dedicated to interrupt requests. When a device signals on

this specific line, the processor halts its activity and executes an interrupt service routine.

Software interrupts:

Software interrupts are usually associated with the software. A simple output operation in

a multitasking system requires software interrupts to be generated so that the processor

may  temporarily  halt  its  activity  and  place  the  data  on  its  data  bus  for  the  peripheral



Write the steps involved in bit-pair recording algorithm for integer division.

he following steps are used for integer division:

1.  Clear  upper  half  of  dividend  register  and  put  dividend  in  lower  half.  Initialize

quotient counter bit to 0

2.  Shift dividend register left 1 bit

3.  If difference is +ve, put it into upper half of dividend and shift 1 into quotient. If –

ve, shift 0 into quotient

  1. If quotient bits<m, goto step 2


Q:- floating-point division uses the following steps:

  Unpack sign, exponent and significands

  Apply exclusive-or operation to signs, subtract the exponents and then divide the


  Normalize, round and shift the result.

  Check the result for overflow.

  Pack the result and report exceptions


Calculate time to read 64 KB (128 sectors) for the following disk parameters.

–180 GB, 3.5 inch disk

–12 platters, 24 surfaces

–7,200 RPM; (4 ms avg. latency)

–6 ms avg. seek (r/w)

–64 to 35 MB/s (internal)

–0.1 ms controller time




Disk latency = average seek time + average rotational delay + transfer time +

controller overhead

= 6 ms + 0.5 x 1/(7200 RPM) /(60000ms/M)) + 64 KB / (64 MB/s) + 0.1 ms

= 6 + 4.2 + 1.0 + 0.1 ms = 11.3 ms

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Replies to This Discussion

Pleas trust me over all paper ase say aya tha our mooaz ke file say koi new question nhe tha

thanks Neelam



this my today paper


also pray for my good result


Thank u nina

Thanks Neelam and Nina...... 

normalization in Floating point representation

DRAM 512 row, and totla time is 8ms and single row refresh time batana tha

function of EPROM

division 45(sub 10) by 5(sub 5) all steps

40 GB HD me kitne platters hote han book se e.g ayi thi

device identificaiton methods w.r.t interrupt handling

cache hit / cache miss

cache memory manamgment system

funtion of ISR

diff b/w Raid level 3 and Raid level 4

write through / write back ?

ALL Final Term Papers Spring 2015 & Past Final Term Papers at One Place from 22 August 2015 ~ 02 September 2015

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Q 1: what will happen when microprocessor creates interrupt?
Q 2: Difference between the radix conversation and Diminished radix complement form?
Q 3: write the steps involved in multiplying of floating point numbers?
Q4: write four major function of the cache management?
Q5: what applicant allows the interrupt handle by CPU?
Q6: 1×8 Memory Cell Array (1D) briefly explains it?
Q7: DRAM is 512 rows and refresh time is 8ms what is the frequency of the average time?
Q8: what is the rotational latency of the 15,000rpms?
Q9: what is normalization in floating point numbers?
Q10: what do understand by “overflow”?


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