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aj mera cs501 ka paper tha us paper main 16 mcq moaz ke solve mcq file sa ae hain or 2 short question bhe moaz ke solve subjective file sa ae hain so friends keep focus on moaz solve mcq's and subjetive file


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azmat bhai subah attempt krny k bad share kren gy............

cs501:current Midterm paper

My paper was as follwes: 

9-10 mcqs were from past papers remaining were new.

Q#1: comparison b/w FALCON-A and SRC w.r.t. registers. (2 marks)
Q#2: Define Exception. 
(2 marks)
Q#3:Write stuctural RTL for movi........ 
(3 marks)
Q#4: Write essential Reset operations..... 
(3 marks)
Q#5: Types of Exception.... 
(5 marks)
Q#6:Stuctural RTL description for shift......
(5 marks)

Cs501 Current Midterm Papers

Paper 1
My today cs501 paper all msqs from past papers except 2 total 20 mcqs. and subjective is
Which register holds the instruction that is being executed? 2marks
Which technique is used for overlapping multiple instructions simultaneously?2 marks
Write the Structural RTL for the "mov" instruction i.e. mov ra, rb. 3marks
Write the Structural RTL for the "mov" instruction i.e. mov ra, rb. 3marks
Write the related timing steps requirements and data path implementations of Instruction Fetch procedure using structural RTL 5marks
How many types of exceptions can occur in a machine? Explain any two of them. 5marks


Paper 2
Full paper Moaz ke files mai se aya hai.....
20 mcq's thae r 6 Question thae
2 marks ke 2 Question
3 marks ke 2 Quuestion
5 mzrks ke bi 2 Question
compare bus width of FALCON-A and SRC
What do you know about Machine Exception?
What function is performed by the reset operation of a processor and differentiate Hard reset and Soft reset?
structural RTL out ra,c2 3marks
Consider the following sequence of the instructions giving through the pipelined version of SRC
200:shl r6,r3,5
204:str r7,30
208:sub r2,r4,r5
2012:add r1,r2,r3
216:id r7,48
.Write the structure RTL description for the uni-bus data path implementation Jump[ra+2] (5 Marks)


Paper 3
MY PAPER
(1)compare the uni bus implementation of FALCON-A with SRC with respect to number of registers. [2 MARKS]

(2) Define external and internal Exception. [2MARKS]

(3) Structural RTL for the out instruction out ra,c2. [3MARKS]

(4)Arrange pipelining verification of SRC [3 MARKS]
ALU operation
Instruction fetch
Memory access
Register write

(5) timing step requirement and data path implementation of instruction fetch in structural RTL [5 MARKS]

(6) how many type of Exception ? define two. [5 MARKS]



Paper 4
Which register store previous calculated value.
Differrence between latency and throughput.
Write two important features of reset operation.
write structural RLT for return instruction ret ra. 
Difference between sigma = (a,b)

Paper 5
My today cs501 paper all msqs from past papers except 2 total 20 mcqs. and subjective is

Which register holds the instruction that is being executed? 2marks

Which technique is used for overlapping multiple instructions simultaneously?2 marks

Write the Structural RTL for the "mov" instruction i.e. mov ra, rb. 3marks

Write the related timing steps requirements and data path implementations of Instruction Fetch procedure using structural RTL 5marks

How many types of exceptions can occur in a machine? Explain any two of them. 5marks


Paper 6
timing step requirement and data path implementation of instruction fetch in structural RTL [5 MARKS]

Structural RTL for the out instruction out ra,c2. [3MARKS]


how many type of Exception ? define two. [5 MARKS]


(4)Arrange pipelining verification of SRC [3 MARKS]

ALU operation

Instruction fetch

Memory access

Register write



Define external and internal Exception. [2MARKS]

compare the uni bus implementation of FALCON-A with SRC with respect to number of registers. [2 MARKS]

Paper 7
What do you know about Machine Exception?

.Write the structure RTL description for the uni-bus data path implementation Jump[ra+2] (5 Marks)

Consider the following sequence of the instructions giving through the pipelined version of SRC
200:shl r6,r3,5
204:str r7,30
208:sub r2,r4,r5
2012:add r1,r2,r3
216:id r7,48

What function is performed by the reset operation of a processor and differentiate Hard reset and Soft reset?

structural RTL out ra,c2 3marks


Paper 8
my paper 
What is NOP instruction and its significance in pipelining? 3 
Which register hold the instruction that is being executed? 2
Write the structural RTL for the mov immediate instruction for the mov immediate instruction for uni-bus data path implement Mov ra,c2 3 marks
structural RTL out ra c2 nu instruction? 5 marks
Which register hold the address of the next instruction to be executed in the processor?
What do you aboyt Machie Exception ? 


Paper 9
My paper was as follwes: 

9-10 mcqs were from past papers remaining were new.

Q#1: comparison b/w FALCON-A and SRC w.r.t. registers. (2 marks)
Q#2: Define Exception. (2 marks)
Q#3:Write stuctural RTL for movi........ (3 marks)
Q#4: Write essential Reset operations..... (3 marks)
Q#5: Types of Exception.... (5 marks)
Q#6:Stuctural RTL description for shift......(5 marks)

Paper 10
Q1. Which register holds the address of the next instruction to be executed in the processor? (2 Marks)
Answer:- 
The program counter (PC) that holds the address of the next instruction in memory that is to be executed.
Write the main functions of the branch instruction
calculate the target address to evolutes the condition
3.Write the Structural RTL for the "mov" instruction i.e. mov ra, rb. 3marks
4.what is the utility of reset operation when it is required (3 marks)
Answer:- (Page 194)
Reset operation is required to change the processor’s state to a known, defined value. The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value.
5. Write the Structural RTL description for un-conditional jump uni-bus data path implementation. jump [ra+c2]. 5 marks
6. solution of data dependencies briefly explain. 5 marks


Paper 11
1.Insrtuction Fetch 2)
2.Arithmetic logic unit 2)
3.Memory access 3)
4.Pipeline Problems 3)
5.Related things steps requirements and data path implementation of IF procedure using RTL 5)
6.Role of step generator in a processor 5)


Paper 12
My Today cs501 Midterm Paper
20 Mcq's from lecture 20,21,22 
Not from Previous Paper 
Subjective
Q1:
structural RTL for mov ra, rb
Q2:
Which register holds the address of the next instruction to b executed in the processor?
Q3:
Write the structural RTL for the mov immediate instruction for the mov immediate instruction for uni-bus data path implementation Movi ra,c2
Q4:
Consider the following sequence of the instructions giving through the pipelined version of SRC
200:shl r6,r3,5
204:str r7,30
208:sub r2,r4,r5
2012:add r1,r2,r3
216:id r7,48
Q5:
Write the structure RTL description for the uni-bus data path implementation Jump[ra+2]
Q6:
Write the Structural RTL for the 'not instruction

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